lan91c100fd Standard Microsystems Corp., lan91c100fd Datasheet
lan91c100fd
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lan91c100fd Summary of contents
Page 1
... LAN83C694 for 10BASE-T and coax 10 Mbps Ethernet networks. The second interface follows the MII (Media Independent Interface) specification draft standard, consisting of 4 bit wide data transfers at the nibble rate. This interface is applicable to 10 Mbps or 100 Mbps networks. Three of the LAN91C100FD’s pins are used to interface to the SMSC DS – LAN91C100FD REV. B LAN91C100FD REV ...
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... FDUPLX bit in the TCR. In order to avoid confusion, the new, broader full duplex function of the LAN91C100FD is designated as Switched Full Duplex, and the TCR bit enabling it is designated as SWFDUP. When the LAN91C100FD is configured for SWFDUP, its transmit and receive paths will operate independently and some CSMA/CD functions will be disabled ...
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... FEATURES................................................................................................................................1 GENERAL DESCRIPTION........................................................................................................1 PIN CONFIGURATION..............................................................................................................4 DESCRIPTION OF PIN FUNCTIONS .......................................................................................5 FUNCTIONAL DESCRIPTION ................................................................................................12 DATA STRUCTURES AND REGISTERS...............................................................................16 BOARD SETUP INFORMATION ............................................................................................46 APPLICATION CONSIDERATIONS .......................................................................................48 OPERATIONAL DESCRIPTION .............................................................................................56 MAXIMUM GUARANTEED RATINGS*....................................................................................56 DC ELECTRICAL CHARACTERISTICS..................................................................................56 TIMING DIAGRAMS ................................................................................................................59 SMSC DS – LAN91C100FD REV. B TABLE OF CONTENTS Page 3 Rev. 03-28-07 ...
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... RD3 38 RD2 39 RD1 40 VDD 41 RD0 42 RD15 43 RD14 44 RD13 45 GND 46 RD12 47 RD11 48 RD10 49 GND 50 ENEEP 51 EEDO 52 SMSC DS – LAN91C100FD REV. B PIN CONFIGURATION and TQFP Page 4 A12 156 A11 155 A10 154 A9 153 A8 152 A7 151 A6 150 A5 149 A4 148 A3 147 A2 146 A1 145 D8 144 VDD ...
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... IS Input. For systems that require address latching, the rising edge of nADS indicates the latching moment for A1-A15 and AEN. All LAN91C100FD internal functions of A1-A15, AEN are latched except for nLDEV decoding. I Input. This active low signal is used to control LAN91C100FD EISA burst mode synchronous bus cycles ...
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... Input. When nDATACS is low, the Data Path can pullup be accessed regardless of the values of AEN, A1- A15 and the content of the BANK SELECT Register. nDATACS provides an interface for bursting to and from the LAN91C100FD 32 bits at a time. Output. 4 µsec clock used to shift data in and out O4 of the serial EEPROM. O4 Output ...
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... RAM. O4 Outputs. Active low signals used to write any byte, word or dword in RAM. O4 Output. This pin is active during LAN91C100FD write memory cycles of receive packets. Iclk An external 25 MHz crystal is connected across these pins TTL clock is supplied instead, it should be connected to XTAL1 and XTAL2 should be left open ...
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... MII management clock. I with Input. Indicates a code error detected by PHY. pulldown Used by the LAN91C100FD to discard the packet being received. The error indication reported for this event is the same as a bad CRC (Receive Status Word bit 13). This pin is ignored when MIISEL is low. ...
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... DMAed to memory or if asserted during the last DMA write to memory. Works for both MII and ENDEC. The typical use of nRXDISC is with the LAN91C100FD in PRMS mode with an external associative memory use for address filtering. *Note: The pin must be asserted for a minimum of 80ns. ...
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... BUS Data INTERFACE UNIT Control RD WR FIFO FIFO FIGURE 1 - LAN91C100FD BLOCK DIAGRAM SMSC DS – LAN91C100FD REV. B PIN SYMBOLS A1-A15, AEN, nBE0-nBE3 D0-D31 RESET, nADS, LCLK, ARDY, nRDYRTN, nSRDY, INTR0- INTR3, nLDEV, nRD, nWR, nDATACS, nCYCLE, W/nR, nVLBUS EEDI, EEDO, EECS, EESK, ENEEP, IOS0-IOS2 ...
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... SYSTEM BUS ADDRESS ADDRESS CONTROL CONTROL LAN91C100FD DATA DATA RA FIGURE 2 - LAN91C100FD SYSTEM DIAGRAM SMSC DS – LAN91C100FD REV. B SERIAL EEPROM 1O Mbps FEAST MII OE,WE RD0-31 OR SRAM 3 4 32kx8 2 1 Page 11 LAN83C69 10BASE-T 10BASE-T INTERFACE 100BASE-T4 INTERFACE CHIP 100BASE-T4 100BASE-TX 100BASE-TX/ INTERFACE 10BASE-T LOGIC/ 10BASE-T Rev ...
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... The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These FIFOs can be accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not Ready' whenever a cycle is initiated that cannot be satisfied by the present state of the FIFO. SMSC DS – LAN91C100FD REV. B FUNCTIONAL DESCRIPTION Page 12 ...
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... When working with an asynchronous bus like ISA, the read and write operations are controlled by the edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle. The leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C100FD clock and, therefore, asynchronous to the bus. ...
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... MIISEL pin reflects the value of this bit and may be used to control external multiplexing logic. Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running clocks. The LAN91C100FD will not rely on the presence of TX25 and RX25 during reset and will use its own internal clock whenever a timeout on TX25 is detected. ...
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... EEPROM EEPROM INTERFACE DATA BUS ADDRESS BUS BUS INTERFACE CONTROL WRITE READ DATA DATA REG REG FIGURE 3 - LAN91C100FD INTERNAL BLOCK DIAGRAM WITH DATA PATH SMSC DS – LAN91C100FD REV FIFO DMA CSMA/CD FIFO TX COMPL FIFO ARBITER MMU DATA ADDRESS BUFFER RAM ...
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... The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS, followed by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The LAN91C100FD does not insert its own source address. On receive, all bytes are provided by the CSMA side. SMSC DS – LAN91C100FD REV. B ...
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... The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C100FD treated transparently as data both for transmit and receive operations. CONTROL BYTE - For transmit packets the CONTROL BYTE is written by the CPU as ODD ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE. If clear, the number of data bytes is even and the byte before the CONTROL BYTE is not transmitted ...
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... EPH STATUS 4 RCR 6 COUNTER 8 MIR A MCR C RESERVED (0) E BANK SELECT A special BANK (BANK7) exists to support the addition of external registers. SMSC DS – LAN91C100FD REV. B HASH VALUE 5-0 MULTICAST TABLE BIT 000 000 010 000 100 111 111 111 NAME TYPE bit 13 bit 12 bit ...
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... BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the register bank in use. The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C100FD. The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2. ...
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... FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C100FD will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted ...
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... TXENA is set high. Fatal errors are: 16 collisions (1/2 duplex mode only) SQET fail and STP_SQET = 1 (1/2 duplex mode only) FIFO Underrun Carrier lost and MON_CSN = 1 (1/2 duplex mode only) Late collision (1/2 duplex mode only) SMSC DS – LAN91C100FD REV. B Page 21 Rev. 03-28-07 ...
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... SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C100FD’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). Otherwise recognizes a receive frame as soon as carrier sense is active ...
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... MEMORY SIZE - This register can be read to determine the total memory size. All memory related information is represented in 256 * M byte units, where the multiplier M is determined by the MCR upper byte. These register default to FFh, which should be interpreted as 256. SMSC DS – LAN91C100FD REV. B NAME TYPE READ ONLY ...
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... The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the Memory Size Multiplier. M=2 for the LAN91C100FD. A value of 04h in the lower byte of the MCR is equal to one 2K page (4 * 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only when the entire memory is being reserved for transmit (i ...
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... INT SEL1-0 - Used to select one out of four interrupt pins. The three unused interrupts are tristated. INT SEL1 BANK 1 OFFSET 2 BASE ADDRESS REGISTER This register holds the I/O address decode option chosen for the LAN91C100FD part of the EEPROM saved setup and is not usually modified during run-time. HIGH A15 A14 BYTE ...
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... Store operations. This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C100FD. SMSC DS – LAN91C100FD REV. B ...
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... During this time attempted read/write operations, other than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C100FD after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 µs. ...
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... Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory. Note 1: Bits N2,N1,N0 bits are ignored by the LAN91C100FD but should be used for command 0 to preserve software compatibility with the LAN91C92 and future devices. They should be zero for all other commands. ...
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... FAILED bit is clear. Note: For software compatibility with future versions, the value read from the ARR after an allocation request is intended to be written into the PNR as is, without masking higher bits (provided FAILED = 0). SMSC DS – LAN91C100FD REV. B NAME TYPE READ/WRITE ...
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... READ - Determines the type of access to follow. If the READ bit is high the operation intended is a read. If the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit high, generates a pre-fetch into the Data Register for read purposes. SMSC DS – LAN91C100FD REV. B NAME TYPE ...
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... DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register. This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C100FD regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre- fetched from memory into the read FIFO ...
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... This bit latches the empty condition, and the bit will stay set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set real time reading of the FIFO empty is desired, the bit should be first cleared and then read. SMSC DS – LAN91C100FD REV. B NAME TYPE ...
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... Note: If the driver uses AUTO RELEASE mode it should enable TX EMPTY INT as well as TX INT. TX EMPTY INT will be set when the complete sequence of packets is transmitted. TX INT will be set if the sequence stops due to a fatal error on any of the packets in the sequence. FIGURE 5 - SMSC DS – LAN91C100FD REV. B STRUCTURE Page 33 INTERRUPT ...
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... Hashing is only a partial group addressing filtering scheme, but being the hash value available as part of the receive status word, the receive routine can reduce the search time significantly. With the proper memory structure, the search is limited to comparing only the multicast addresses that have the actual hash value in question. SMSC DS – LAN91C100FD REV. B NAME TYPE ...
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... CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. OFFSET C EARLY RCV REGISTER HIGH BYTE 0 0 LOW RCV 0 BYTE DISCRD 0 0 SMSC DS – LAN91C100FD REV. B NAME TYPE READ/WRITE MDOE NAME TYPE READ ONLY 1 1 ...
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... ERCV THRESHOLD, ERCV INT bit of the INTERRUPT STATUS REGISTER is set. BANK7 OFFSET 0 THROUGH 7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C100FD when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE LOW BYTE CYCLE ...
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... RELEASE packet number command to free up the memory used by this packet. Remove packet number from completion FIFO by writing TX INT Acknowledge Register. SMSC DS – LAN91C100FD REV. B COMPLETION The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state ...
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... CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC DS – LAN91C100FD REV. B MAC SIDE A packet is received with matching address. Memory is requested from MMU. number is assigned to it. Additional memory is requested if more pages are needed ...
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... Call TX INTR or TXEMPTY INTR Get Next TX Packet Available for Transmission? Yes Call ALLOCATE Yes Call EPH INTR FIGURE 6 - INTERRUPT SERVICE ROUTINE SMSC DS – LAN91C100FD REV. B ISR Save Bank Select & Address Ptr Registers Mask SMC91C100FD Interrupts Read Interrupt Register No RX INTR? Yes TX INTR? ...
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... SMSC DS – LAN91C100FD REV INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM No Yes Destination Multicast? Read Words from RAM for Address Filtering Address No Yes Filtering Pass? No Yes Status Word OK? Do Receive Lookahead Get Copy Specs from Upper Layer ...
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... SMSC DS – LAN91C100FD REV INTR Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg. Write Into Packet Number Register Write Address Pointer Register Read Status Word from RAM Yes TX Status No OK? Immediately Issue "Release" Command Update Variables Acknowledge TXINTR ...
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... TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) FIGURE 9 - TXEMPTY INTR (ASSUMES AUTO RELEASE OPTION SELECTED) SMSC DS – LAN91C100FD REV. B TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 1 TXEMPTY = X & TXINT = 1 (Everything went through (Transmission Failed) Read Pkt. # Register & Save ...
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... Write Allocated Packet into Write Address Pointer Register Copy Part of TX Data Packet Set "Ready for Packet" Flag Return Buffers to Upper Layer FIGURE 10 - DRIVE SEND AND ALLOCATE ROUTINES SMSC DS – LAN91C100FD REV. B ALLOCATE Issue "Allocate Memory" Command to MMU Read Interrupt Status Register Yes ...
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... In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the TX DONE PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet numbers being transmitted. The numbers are queued by the LAN91C100FD and provided back to the CPU as their transmission completes. ...
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... AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed successfully. Note: The pointer register is shared by any process accessing the LAN91C100FD memory. In order to allow processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt ...
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... In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C100FD. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, INTERRUPT) that can always be used regardless of the EEPROM based value being programmed ...
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... No other bits of the LAN91C100FD can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads. Note EEPROM is connected to the LAN91C100FD, for example for some embedded applications, the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted ...
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... VL Local Bus 32 Bit SystemsVL Local Bus 32 bit systemsVL Local Bus 32 bit systems On VL Local Bus and other 32 bit embedded systems the LAN91C100FD is accessed bit peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or dword instructions ...
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... VCC nRD nWR GND A1 nVLBUS OPEN nDATACS SMSC DS – LAN91C100FD REV. B NOTES created typically by using nADS delayed by one LCLK. Typically uses the interrupt lines on the ISA edge connector of VL bus 32 bit data bus. The bus byte(s) used to access the device are a ...
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... VL BUS W/nR A2-A15 LCLK M/nIO nRESET IRQn D0-D31 nRDYRTN nBE0-nBE3 nADS delay 1 LCLK nLRDY nLDEV SMSC DS – LAN91C100FD REV. B W/nR A2-A15 LCLK AEN RESET LAN91C100FD INTR0-INTR3 D0-D31 nRDYRTN nBE0-nBE3 nADS nCYCLE nSRDY O.C. simulated O.C. FIGURE 13 - LAN91C100FD ON VL BUS Page 50 nLDEV Rev. 03-28-07 ...
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... HIGH-END ISA OR NON-BURST EISA MACHINES On ISA machines, the LAN91C100FD is accessed bit peripheral. No support for XT (8 bit peripheral) is provided. The signal connections are listed in the following table: Table 4 - High-End ISA or Non-Burst EISA Machines Signal Connectors ISA BUS LAN91C100FD SIGNAL SIGNAL A1-A15 ...
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... ISA BUS A1-A15, AEN RESET VCC D0-D15 nIRQ nIORD nIOWR A0 nSBHE nIOCS16 SMSC DS – LAN91C100FD REV. B A1-A15, AEN RESET nBE2, nBE3 D0-D15 LAN91C100FD INTR0-INTR3 nRD nWR nBE0 nBE1 nLDEV O.C. FIGURE 14 - LAN91C100FD ON ISA BUS Page 52 Rev. 03-28-07 ...
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... EISA 32 BIT SLAVEEISA 32 bit slave On EISA the LAN91C100FD is accessed bit I/O slave, along with a Slave DMA type "C" data path option I/O slave, the LAN91C100FD uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is externally derived from nCMD edges. Given that the access will be at least 1 clocks (more than 180ns at least) there is no need to negate EXRDY, simplifying the EISA interface implementation ...
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... BCLK wide). EISA Bus Clock. Data transfer clock for DMA bursts. DMA Acknowledge. Active during Slave DMA cycles. Used by the LAN91C100FD as nDATACS direct access to data path. Indicates the direction and timing of the DMA cycles. High during LAN91C100FD writes, low during LAN91C100FD reads. ...
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... EISA BUS LA2-LA15 RESDRV AEN M/nIO D0-D31 IRQn nBE0-nBE3 nCMD LATCH + gates nWR BCLK nSTART nEX32 O.C. FIGURE 15 - LAN91C100FD ON EISA BUS SMSC DS – LAN91C100FD REV. B A2-A15 RESET AEN D0-D31 INTR0-INTR3 LAN91C100FD nBE0-nBE3 nRD nWR LCLK nADS nLDEV Page 55 Rev. 03-28-07 ...
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... Input Buffer CLK Low Input Level High Input Level Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage IP Type Buffers Input Current ID Type Buffers Input Current SMSC DS – LAN91C100FD REV. B SYMBOL MIN TYP MAX V 0.8 ILI V 2.0 IHI V 0.8 ...
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... Low Output Level Output Leakage O24 Type Buffer Low Output Level High Output Level Output Leakage I/O24 Type Buffer Low Output Level High Output Level Output Leakage Supply Current Active Supply Current Standby SMSC DS – LAN91C100FD REV. B MIN TYP MAX UNITS ...
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... CAPACITANCE T = 25EC 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance CAPACITIVE LOAD ON OUTPUTS nARDY, D0-D31 (non VLBUS) D0-D31 in VLBUS All other outputs SMSC DS – LAN91C100FD REV LIMITS MIN TYP MAX OUT 240 ...
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... High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE3 Hold after nADS Rising SMSC DS – LAN91C100FD REV. B TIMING DIAGRAMS A1-15, AEN, nBE0-nBE3 valid t3 t5 D0-D31 valid MIN 25 20 ...
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... A1-A15, AEN, nBE0-nBE3 Hold After nRD, nWR Inactive (Assuming nADS Tied Low) t3 nRD Low to Valid Data t4 nRD High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive SMSC DS – LAN91C100FD REV D0-D31 valid MIN TYP MAX 25 20 ...
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... Setup to LCLK Falling t15 nRDYRTN Hold after LCLK Falling t17 nCYCLE High and W/nR High Overlap t19 Data Delay from LCLK Rising (Read) Note *: (holdt.) Note **: (Setupt.) SMSC DS – LAN91C100FD REV. B t12 t17 t20 t18 a b PARAMETER t12 t17 t19 ...
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... W/nR Setup to nCYCLE Active t17A W/nR Hold after LCLK Rising with nLRDY Active t18 Data Setup to LCLK Rising (Write) t20 Data Hold from LCLK Rising (Write) t21 nLRDY Delay from LCLK Rising SMSC DS – LAN91C100FD REV A1-A15, AEN, nBE0-nBE3 t25 MIN TYP 10 15 ...
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... W/nR Setup to nCYCLE Active t20 Data Hold from LCLK Rising (Read) t21 nLRDY Delay from LCLK Rising t23 nRDYRTN Setup to LCLK Rising t24 nRDYRTN Hold after LCLK Rising SMSC DS – LAN91C100FD REV A1-A15, AEN, nBE0-nBE3 t8 t10 t16 t11 MIN 10 15 ...
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... Write – RD0-RD31 Hold after nRWE0-nRWE3 Rising t39 Write – nRWE0-nRWE3 Pulse Width t38 Read – RA2-RA16 Valid to RD0-RD31 Valid t51 Read – RD0-RD31 Hold after RA2-RA16 Change SMSC DS – LAN91C100FD REV. B t35 t38 t39 t39 t36 t37 t51 t34 ...
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... RXD0-RXD3 RX25 RX_DV RX_ER PARAMETER t27 TXD0-TXD3, TXEN100 Delay from TX25 Rising t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising SMSC DS – LAN91C100FD REV. B t30 MIN TYP t27 t27 FIGURE 26 - MII INTERFACE MIN ...
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... L when measured at the gauge plane 0.25mm above the seating plane, is 0.6mm. Details of pin 1 identifier are optional but must be located within the zone indicated Controlling dimension: millimeter FIGURE 27 - 208 PIN QFP PACKAGE OUTLINES SMSC DS – LAN91C100FD REV 105 ...
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... Dimension for foot length L measured at the gauge plane 0.25mm above the seating plane, is 0.78-1.08mm. Details of pin 1 identifier are optional but must be located within the zone indicated. 5 FIGURE 28 - 208 PIN TQFP PACKAGE OUTLINES SMSC DS – LAN91C100FD REV. B REMARK NOM MAX Overall Package Height 1 ...