lan91c100fd Standard Microsystems Corp., lan91c100fd Datasheet - Page 31

• Manufacturer Part Number: lan91c100fd
• Description: Lan91c100fd Rev. B Feast Fast Ethernet Controller With Full Duplex Capability
• Manufacturer: Standard Microsystems Corp.

Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the last pre-fetched).
This allows any interrupt routine that uses the pointer, to save it and restore it without affecting the process being
interrupted. The Pointer Register should not be loaded until the Data Register FIFO is empty. The NOT EMPTY bit of this register
can be read to determine if the FIFO is empty. On reads, if IOCHRDY is not connected to the host, the Data Register should not
be read before 370ns after the pointer was loaded to allow the Data Register FIFO to fill.
If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.
ETEN - When set enables EARLY Transmit underrun detection. Normal operation when clear.
NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the FIFO is empty
before loading a new pointer value. This is a read only bit.
Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value.
BANK 2
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C100FD regardless
of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-
fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through
the Data Low or Data High registers. The order to and from the FIFO is preserved. Byte, word and dword accesses can be
mixed on the fly in any order.
This register is mapped into two consecutive word locations to facilitate double word move operations regardless of the
actual bus width (16 or 32 bits). The DATA register is accessible at any address in the 8 through Ah range, while the
number of bytes being transferred is determined by A1 and nBE0-nBE3. The FIFOs are 12 bytes each.
BANK 2
SMSC DS – LAN91C100FD REV. B
RX_DISC
8 THROUGH Bh
OFFSET
INT
X
X
0
OFFSET
C
ERCV INT
X
X
0
INTERRUPT STATUS REGISTER
EPH INT
X
X
DATA REGISTER
0
NAME
NAME
RX_OVRN
INT
X
X
0
DATA HIGH
DATA LOW
Page 31
ALLOC INT
X
X
0
READ ONLY
READ/WRITE
TX EMPTY
TYPE
TYPE
INT
X
X
1
TX INT
X
X
0
SYMBOL
SYMBOL
DATA
IST
RCV INT
X
X
0
Rev. 03-28-07