lan91c100fd Standard Microsystems Corp., lan91c100fd Datasheet - Page 24

• Manufacturer Part Number: lan91c100fd
• Description: Lan91c100fd Rev. B Feast Fast Ethernet Controller With Full Duplex Capability
• Manufacturer: Standard Microsystems Corp.

BANK 0
MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU to reserve memory to be used
later for transmit, limiting the amount of memory that receive packets can use. When programmed for zero, the memory
allocation between transmit and receive is completely dynamic. When programmed for a non-zero value, the allocation is
dynamic if the free memory exceeds the programmed value, while receive allocation requests are denied if the free
memory is less or equal to the programmed value. This register defaults to zero upon reset. It is not affected by the RESET
MMU command.
The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY CURRENTLY IN USE. If the
memory allocated for transmit plus the reserved space for transmit is required to be constant (rather than grow with
transmit allocations) the CPU should update the value of this register after allocating or releasing memory.
The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the Memory
Size Multiplier. M=2 for the LAN91C100FD. A value of 04h in the lower byte of the MCR is equal to one 2K page (4 * 256
*2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only when
the entire memory is being reserved for transmit (i.e., low byte of MCR = FFh).
BANK1
The Configuration Register holds bits that define the adapter configuration and are not expected to change during run-time.
This register is part of the EEPROM saved setup.
MII SELECT - Used to select the network interface port. When set, the LAN91C100FD will use its MII port and interface a
PHY device at the nibble rate. When clear, the LAN91C100FD will use its 10 Mbps ENDEC interface. This bit drives the MII
SEL pin. Switching between ports should be done with transmitter and receiver disabled and no transmit/receive packets in
progress.
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not
ready for a transfer. When clear, negates IOCHRDY for two to three clocks on any cycle to the LAN91C100FD.
SMSC DS – LAN91C100FD REV. B
OFFSET
OFFSET
HIGH
BYTE
BYTE
HIGH
BYTE
BYTE
LOW
LOW
A
0
SELECT
MII
0
0
1
1
1
CONFIGURATION REGISTER
MEMORY CONFIGURATION
0
0
0
0
0
MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M)
REGISTER
NAME
NAME
1
0
1
1
Page 24
NO WAIT
Reserved
1
0
0
1
MEMORY SIZE MULTIPLIER
READ/WRITE
READ/WRITE
Lower Byte -
Upper Byte -
READ ONLY
0
0
0
0
TYPE
TYPE
INT SEL1
STEP
FULL
1
0
0
0
INT SEL0
0
0
0
0
0
SYMBOL
SYMBOL
MCR
CR
SELECT
AUI
1
0
0
1
Rev. 03-28-07