lan9303 Standard Microsystems Corp., lan9303 Datasheet - Page 116

• Manufacturer Part Number: lan9303
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Single Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Revision 1.3 (08-27-09)
8.4.4.2
8.4.4.3
8.4.5
re-runs the Auto-negotiation using the new default values of the
Advertisement Register (PHY_AN_ADV_x)
Note: Each of these PHY registers is written in its entirety, overwriting any previously changed bits.
Virtual PHY Registers Synchronization
Some PHY register defaults are based on configuration straps. In order to maintain consistency
between the updated configuration strap registers and the Virtual PHY registers, the
Negotiation Advertisement Register
( V P H Y _ S P E C I A L _ C O N T R O L _ S TAT U S )
(VPHY_BASIC_CTRL)
The
defaults as detailed in
(VPHY_AN_ADV)," on page
The
with the new defaults as detailed in
(VPHY_SPECIAL_CONTROL_STATUS)," on page
The
detailed in
Additionally, the
Auto-negotiation using the new default values of the
Register (VPHY_AN_ADV)
Note: Each of these VPHY registers is written in its entirety, overwriting any previously changed bits.
LED and Manual Flow Control Register Synchronization
Since the defaults of the
(MANUAL_FC_1),
Control Register (MANUAL_FC_0)
these registers with their new default values.
Register Data
Optionally following the configuration strap values, the EEPROM data may be formatted to allow
access to the device’s parallel, directly writable registers. Access to indirectly accessible registers (e.g.
Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost of
EEPROM space).
This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a
value of A5h, the data that follows is recognized as a sequence of bursts. Otherwise, the EEPROM
Loader is finished, will go into a wait state, and clear the
in the
The data at EEPROM byte 13 and above should be formatted in a sequence of bursts. The first byte
is the total number of bursts. Following this is a series of bursts, each consisting of a starting address,
count, and the count x 4 bytes of data. This results in the following formula for formatting register data:
8-bits number_of_bursts
repeat (number_of_bursts)
Following the writes to the PHY registers, the PMI registers are reset back to their default values.
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
16-bits {starting_address[9:2] / count[7:0]}
repeat (count)
EEPROM Command Register
8-bits data[31:24], 8-bits data[23:16], 8-bits data[15:8], 8-bits data[7:0]
Section 13.2.6.1, "Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)," on page
Restart Auto-Negotiation (PHY_RST_AN)
Port 2 Manual Flow Control Register
are written when the EEPROM Loader is run.
LED Configuration Register
Section 13.2.6.5, "Virtual PHY Auto-Negotiation Advertisement Register
register to determine the new Auto-negotiation results.
176.
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
DATASHEET
are based on configuration straps, the EEPROM Loader reloads
(E2P_CMD). This can optionally generate an interrupt.
(VPHY_AN_ADV),
Section 13.2.6.8, "Virtual PHY Special Control/Status Register
116
register to determine the new Auto-negotiation results.
, a n d
182.
(LED_CFG),
Virtual PHY Auto-Negotiation Advertisement
V i r t u a l P H Y B a s i c C o n t r o l R e g i s t e r
Virtual PHY Special Control/Status Register
(MANUAL_FC_2), and
EEPROM Controller Busy (EPC_BUSY)
bit is set in this register. This re-runs the
Port 1 Manual Flow Control Register
is written with the new defaults as
Port x PHY Auto-Negotiation
SMSC LAN9303/LAN9303i
is written with the new
Port 0 Manual Flow
Virtual PHY Auto-
Datasheet
is written
170.
bit