lan9221 Standard Microsystems Corp., lan9221 Datasheet - Page 48

• Manufacturer Part Number: lan9221
• Description: High-performance 16-bit Non-pci 10/100 Ethernet Controller With Variable Voltage I/o
• Manufacturer: Standard Microsystems Corp.

Revision 2.6 (12-04-08)
3.10.3.2
3.11
PHY REG 0.15
SOURCE
RESET
PHY_RST
nRESET
SRST
Energy Detect Power-Down
This power-down mode is activated by setting the Phy register bit 17.13 to 1. Please refer to
5.5.8, "Mode Control/Status," on page 123
no energy is present on the line, the PHY is powered down, with the exception of the management
interface, the SQUELCH circuit and the ENERGYON logic. The ENERGYON logic is used to detect
the presence of valid energy from 100Base-TX, 10Base-T, or Auto-negotiation signals
In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is
transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and
the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts
the INT7.1 bit of the register defined in
ENERGYON interrupt is enabled, this event will cause an interrupt to the host. The first and possibly
the second packet to activate ENERGYON may be lost. When 17.13 is low, energy detect power-down
is disabled.
The LAN9221/LAN9221i has four reset sources:
Table 3.11
Note: For proper operation, the LAN9221/LAN9221i must be reset on power-up via the hardware
Note 3.17 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic
Note 3.18 After a power-up, nRESET or SRST, the LAN9221/LAN9221i will automatically check for
Note 3.19 HBI - “Host Bus Interface”, NASR - Not affected by software reset.
Detailed Reset Description
Hardware Reset Input Pin (nRESET)
Soft Reset (SRST)
PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)
PHY Soft Reset via PHY Basic Control Register (PHY REG 0.15)
PLL
reset input (nRESET) or soft reset (SRST). To accomplish this, nRESET should be asserted
for the minimum period of 30ms at power-up. Alternatively, a soft reset may be performed
following power-up by setting the SRST bit of the HW_CFG register once the READY bit in the
PMT_CTRL register has been set. Refer to
and
X
shows the effect of the various reset sources on the LAN9221/LAN9221i's circuitry.
Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data.
the presence of an external EEPROM. After any of these resets the application must verify
that the EPC Busy Bit (E2P_CMD, bit 31) is cleared before attempting to access the
EEPROM, or change the function of the GPO/GPIO signals, or before modifying the
ADDRH or ADDRL registers in the MAC.
Section 3.11.3, "Soft Reset (SRST)"
Note
HBI
3.19
X
X
Table 3.11 Reset Sources and Affected Circuitry
REGISTERS
Note 3.19
NASR
X
DATASHEET
MIL
X
X
Section 5.5.11, "Interrupt Source Flag," on page
for additional information on this register. In this mode when
48
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
MAC
for additional information.
X
X
Section 3.11.1, "Hardware Reset Input (nRESET)"
Note 3.17
PHY
X
X
X
EEPROM MAC
Note 3.18
RELOAD
ADDR.
X
X
SMSC LAN9221/LAN9221i
LATCHED
CONFIG.
STRAPS
126. If the
Datasheet
X
Section