peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 282

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
DPLA
WFA
XRNR
RRNR
DPLL Asynchronous
This bit is only valid if the receive clock is recovered by the DPLL and
FM0, FM1 or Manchester data encoding is selected. It is set when the
DPLL has lost synchronization. In this case reception is disabled
(receive abort condition) until synchronization has been regained. In
addition transmission is interrupted in all cases where transmit clock is
derived from the DPLL (clock mode 3a, 7a). Interruption of transmission
is performed the same way as on deactivation of the CTS signal.
DPLA=’0’
DPLA=’1’
Wait For Acknowledgement
This status bit is significant in Automode only. It indicates whether the
Automode state machine expects an acknowledging I- or S-Frame for a
previously sent I-Frame.
WFA=’0’
WFA=’1’
Transmit RNR Status
This status bit is significant in Automode only. It indicates the receiver
status of the local station (SCC).
XRNR=’0’
XRNR=’1’
Received RNR Status
This status bit is significant in Automode only. It indicates the receiver
status of the remote station.
RRNR=’0’
RRNR=’1’
DPLL is synchronized.
DPLL is asynchronous (re-synchronization process is
started automatically).
No acknowledge I/S-Frame is expected.
The Automode state machine is waiting for an
achnowledging S- or I-Frame.
The receiver is ready and will automatically answer poll-
frames with a S-Frame with ’receiver-ready’ indication.
The receiver is NOT ready and will automatically answer
poll-frames with a S-Frame with a ’receiver-not-ready’
indication.
The remote station receiver is ready.
The remote receiver is NOT ready.
(A ’receiver-not-ready’ indication was received from the
remote station)
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Detailed Register Description
PEB 20534
PEF 20534
(hdlc mode)
(hdlc mode)
(hdlc mode)
(all modes)
2000-05-30