peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 346

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
RFS
TIME
RSC
PERR
PCE
Receive Frame Start Interrupt
This bit is set to ’1’, if the beginning of a valid frame is detected by the
receiver. A valid frame is detected either if a valid address field is
recognized (in all operating modes with address recognition) or if a start
flag is recognized (in all operating modes with no address recognition).
Time Out Interrupt
This bit is set to ’1’, if the time out limit is exceeded, i.e. no new character
was received in a programmable period of time (refer to register CCR1
bit fields ’TOIE’ and ’TOLEN’ for more information).
Receive Status Change Interrupt
This bit is valid in HDLC Automode only.
It is set to ’1’, if a status change of the remote station receiver has been
detected by receiving a S-frame with receiver ready (RR) or receiver not
ready (RNR) indication. Because only a status change is indicated via
this interrupt, the current status can be evaluated by reading bit ’RRNR’
in status register STAR.
Parity Error Interrupt
This bit is only valid if parity checking/generation is enabled via bit
’PARE’ in register CCR2.
It is set to ’1’, if a character with wrong parity has been received. If
enabled via bit ’RFDF’, this error status is additionally stored in the
receive status byte generated for each receive character.
Protocol Error Interrupt
This bit is valid in HDLC Automode only.
It is set to ’1’, if the receiver has detected a protocol error, i.e. one of the
following events occured:
• an S- or I-frame was received with wrong N(R) counter value;
• an S-frame containing an I-control field was received.
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Detailed Register Description
(async/bisync modes)
(async mode)
(hdlc mode)
PEB 20534
PEF 20534
(hdlc mode)
(hdlc mode)
2000-05-30