m66257fp Renesas Electronics Corporation., m66257fp Datasheet
m66257fp
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m66257fp Summary of contents
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... Line Memory (FIFO) Description The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit double configuration which uses high-performance silicon gate CMOS process technology. It allows simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over multiple lines ...
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... M66257FP Pin Arrangement Data output REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page M66257FP 1 GND RRES RCK WRES WCK GND ...
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... M66257FP Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature Recommended Operating Conditions Item Supply voltage Supply voltage Operating ambient temperature Electrical Characteristics Item "H" input voltage "L" input voltage "H" output voltage " ...
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... M66257FP Function When write enable input WE is "L", the contents of data inputs D in synchronization with rise edge of write clock input WCK. At this time, the write address counter of 1-line delay data only memory is also incremented simultaneously. The write functions given below are also performed in synchronization with rise edge of WCK. ...
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... M66257FP Switching Characteristics Item Access time Output hold time Output enable time Output disable time Timing Conditions Item Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) " ...
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... M66257FP Test Circuit pF Input pulse level Input pulse rise/fall time Decision voltage input: 1.3 V Decision voltage output: 1.3 V (However, t decision) The load capacitance C includes the floating capacitance of connection and the input capacitance of probe. L Parameter t ODIS (LZ) t ODIS (HZ) ...
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... M66257FP Operating Timing Write Cycle Cycle n Cycle WCK t t WCK WCKH (n) Write Reset Cycle Cycle n − 1 Cycle n WCK t t WCK NRESH WRES − REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page Cycle Disable cycle ...
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... M66257FP Read Cycle Cycle n Cycle RCK t t RCK RCKH RE Q0n (n) Q1n Read Reset Cycle Cycle n − 1 Cycle n RCK t t RCK NRESH RRES Q0n (n − 1) Q1n t ON REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page Cycle Disable cycle RCKL REH ...
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... M66257FP Note at WCK Stop n cycle cycle WCK t WCK (n) Period of writing data (n) into memory Input data cycle is read at the rising edge after WCK of n cycle. Writing operation starts in the "L" period of WCK cycle and ends at the rising edge after cycle. ...
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... M66257FP Shortest Read of Data "n" Written in Cycle n (Cycle n − read side should be started after end of cycle write side) When the start of cycle n − read side is earlier than the end of cycle write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n − invalid. ...
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... M66257FP Application Example Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction M66257 Line ( image data 1-line delay Q Q 2-line delay Primary scanning direction REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page Line n image data Q 00 ...
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... M66257FP Package Dimensions JEITA Package Code RENESAS Code P-SSOP36-8.4x15-0.80 PRSP0036GA Index mark REJ03F0251-0200 Rev.2.00 Sep 14, 2007 Page Previous Code MASS[Typ.] 36P2R-A 0. NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...