vsc7217 Vitesse Semiconductor Corp, vsc7217 Datasheet
vsc7217
Related parts for vsc7217
vsc7217 Summary of contents
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... Optional Encoder/Decoder Bypass Operation TM • “ASIC-Friendly ” Timing Options for Transmitter Parallel Input Data • Elastic Buffers for Intra/Inter-Chip Cable Deskewing and Channel-to-Channel Align- ment • Tx/Rx Rate Matching via IDLE Insertion/ Deletion VSC7217 Block Diagram TRANSMITTER PTXEND 8 8 TD(7:0) 8B/10B C/ ...
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... TTL (using REFCLKP and leaving REFCLKN open). Clock Synthesizer Depending on the state of the DUAL input, the VSC7217 clock synthesizer multiplies the reference fre- quency provided on the REFCLK input by 10 (DUAL is LOW (DUAL is HIGH) to achieve a baud rate clock between 0.98GHz and 1.36 GHz. The on-chip Phase Lock Loop (PLL) uses a single external 0.1 F capacitor, connected between CAP0 and CAP1, to control the Loop Filter ...
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... Transmitter Functional Description Transmitter Data Bus Each VSC7217 transmit channel has an 8-bit input transmit data character, Tn(7:0), and two control inputs, C/Dn and WSENn. The C/Dn input determines whether a normal data character or a special “K-character” is transmitted, and the WSENn input initiates transmission of a 16-character “Word Sync Sequence” used to align the receive channels ...
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... Figure 4: Transmit Timing, TMODE(2:0) = 11X (“ASIC-Friendly” Timing TBCA or TBCn Tn(7:0) C/Dn Valid WSENn Page 4 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Valid Valid Valid 180 Valid VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 Valid Valid o o 270 360 Valid G52325-0, Rev. 3.0 6/14/00 ...
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... Fibre Channel (VSC7125) and Gigabit Ethernet (VSC7135) markets. Word Sync Generation The VSC7217 can perform channel alignment (also referred to as “word alignment” or “word sync”). In other words, the four receive data output streams are aligned such that the same 4-byte word presented to the G52325-0, Rev ...
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... W10 K28.5+ K28.5- K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ Serializer VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 W11 W12 W13 W14 W15 W16 0x03 0x04 K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- D3 ...
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... Preliminary Datasheet VSC7217 mary or redundant serial input as the data source for that channel. When RXP/RC is HIGH, the C channel serial data source is PRXC. When LBENn(1:0)=10, the channel’s transmitter is looped back and becomes the serial data source regardless of the state of RXP/Rn (see Table 4). ...
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... Re-synchronization is always enabled and cannot be turned off when ENDEC is HIGH. After character re-synchronization the VSC7217 ensures that within a link, the 8-bit data sent to the transmitting VSC7217 will be recovered by the receiving VSC7217 in the same bit locations as the transmitter (e.g., Tn(7:0) = Rn(7:0)). When ENDEC is LOW, “Comma” detection and alignment are enabled only if KCHAR is HIGH ...
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... If DUAL is LOW, the data is clocked out of the VSC7217 only on the rising edge of the selected word clock at 1/10th the baud rate. Timing waveforms for the output data and status are shown in Figure 6, Figure 7 and Figure 8. ...
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... REFCLK) steadily drifts in phase relative to the word clock. To accommodate frequency differences between a transmitter’s REFCLK and the word clock, the VSC7217 can automatically perform rate matching by either deleting or duplicating IDLE characters. The FLOCK input must be LOW to enable rate matching which, based on how the WSI input is connected, can either be performed in each channel individually or can be performed in parallel across a group of channels that are word-aligned ...
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... Sync Sequence (either K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+) as the synchronization point model for understanding, consider the case where a VSC7217 transmitter sends 32 bits of data to the receiver via copper media, which has small cable length differences, causing a channel-to-channel skew. All transmit channels that are to be word-aligned transmit the Word Sync Sequence in parallel ...
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... Using Multiple VSC7217s in Parallel Multiple VSC7217s can be used in parallel to form wider bus widths. In order for word alignment to func- tion correctly across multiple devices, each transmit channel’s input data must be transmitted on a common clock, and each receive channel’s output data must also be aligned to a common word clock. This requires that all transmitting devices use either the same or identical REFCLKs, and that TMODE(2:0)=000 (inputs timed to REFCLK) or TMODE(2:0)=1X0 (inputs timed to TBCA) ...
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... IDLEs will have to be added to or dropped from all the channels at the same time. In order to implement this, one VSC7217 is arbitrarily chosen as the “Master” and its WSO output is driven to the WSI inputs of all the receiving VSC7217s, including itself. WSO is asserted prior to the VSC7217 adding/dropping IDLEs so all the VSC7217s will operate simultaneously. WSO uses a simple 3-bit serial protocol, synchronous to the Master channel’ ...
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... A state diagram for the invalid transmission counter is shown in Figure 10. The VSC7217 receiver will stay in the LOSS_OF_SYNC state until a valid Comma pattern is detected. Note that the RESYNC state is entered whenever the 10B framing boundary is changed, and whenever the Word Sync Sequence is received ...
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... Preliminary Datasheet VSC7217 Link Status Outputs The receiver ERRn, KCHn and IDLEn outputs indicate status for each channel as shown below in Table 7. Since this status is encoded, multiple conditions could occur simultaneously so the states are prioritized as indicated (1 being highest priority). For example, if both Out-of-Band and Disparity Errors occur, only an Out-of-Band Error is reported because it has higher priority ...
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... When LBENn(1:0)=10, Serial Loopback mode is selected. The transmitter’s serial transmit data is inter- nally connected to the receiver’s CRU input. The serial loopback paths are labelled LBTXn in the VSC7217 block diagram on the first page. This allows parallel data on Tn(7: encoded, serialized, looped back, deserialized and decoded ...
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... Preliminary Datasheet VSC7217 Figure 11: Parallel Loopback Mode Operation LBENn(1:0) RXP/Rn LBTXn Clk/Data PRXn+ Recovery PRXn- RRXn+ RRXn- PSDETn RSDETn RECEIVER BIST PTXENn 1 8 Gen 8B/10B Tn(7:0) Encode C/Dn 0 WSENn RTXENn REFCLK 0 1 TRANSMITTER KCHAR 0 BIST Built-In Self-Test Operation Built-In Self-Test operation is enabled when the BIST input is HIGH, which causes TMODE(2: internally set to 000 ...
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... In general, the VSC7217 low-speed parallel interfaces can be configured so that there are input and output signals that are compatible with their VSC7211 and VSC7214 counterparts. On the transmit interface, the sig- nals Tn(7:0) and C/Dn behave identically on the VSC7217 as long as the input timing is referenced to REF- CLK (e.g., TMODE(2:0)=000). On the receive interface, the signals Rn(7:0), ERRn, KCHn and IDLEn behave identically on the VSC7217 as long as the four receive channels present output data centered around REFCLK (RMODE(1:0)=00) or timed to RCLKA/RCLKNA (RMODE(1:0)=10) ...
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... The VSC7217 should be configured with RMODE(1:0)=00, FLOCK=1, and WSI connected to its own WSO or to the WSO of another VSC7217 if multiple devices are to be used in parallel. The WSI connection allows word alignment to occur, and the FLOCK connection inhibits IDLE insertion/deletion ...
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... Valid Valid Valid Valid Min Max 1.5 — 1.0 — VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 Valid Valid Units Conditions ns Measured between the valid data level of the input and the 1.4V point of REFCLK or TBCn. ns G52325-0, Rev. 3.0 6/14/00 ...
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... Preliminary Datasheet VSC7217 Figure 15: Transmit Input Timing Waveforms with TMODE = 11X (“ASIC-Friendly” Timing) TBCn (or TBCA) Internal Clock (from PLL) Tn(7:0) C/Dn WSENn Table 10: Transmit Input AC Characteristics with TMODE = 11X Parameters Description Input Skew relative to the rising T S edge of TBCn or TBCA Figure 16: Transmit Serial Timing Waveforms ...
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... PER CQ_max T CQ_max T CQ_min Valid Valid Min -1. 1. PER CQ_max PER 50 50 VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 T PER T QC_min Valid Max Units Conditions RMODE = Bit Clock RMODE = Bit Clock ns T PER T QC_min Valid ...
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... Preliminary Datasheet VSC7217 Figure 19: RCLKn and RCLKNn Timing Waveforms with DUAL = 1 RCLKn RCLKNn Table 14: General Receive AC Characteristics Parameters Description Delay Between Rising Edge T of RCLKn to Rising Edge 3 of RCLKNn RCLKn to RCLKNn Skew Delay = ----------- - f baud Period of RCLKn and T 4 RCLKNn Deviation of ...
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... VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 V IH(MIN) V IL(MAX) Conditions DUAL = 0 DUAL = 1 | REFCLK (Tx) - REFCLK (Rx max offset between Tx and Rx device REFCLKs on one serial link. Measured at 1.4V. Between V and V . IL(MAX) IH(MIN) Peak-to-peak jitter at VSC7217 REFCLK input. G52325-0, Rev. 3.0 6/14/00 ...
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... Preliminary Datasheet VSC7217 Figure 21: Parametric Measurement Information Serial Input Rise and Fall Time T r Receiver Input Eye Diagram Jitter Tolerance Mask Serial Output Load G52325-0, Rev. 3.0 6/14/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION TTL Input and Output Rise and Fall Time ...
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... DD — 1.5 0.7 — — DD 450 — 1100 200 — 1300 3.14 — 3.47 — 3.0 3.5 — 910 1000 + Tx Vout - Tx VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 Units Conditions -1.0mA +1.0mA OL When set to high-impedance A state through JTAG =2. =0. ...
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... Preliminary Datasheet VSC7217 Absolute Maximum Ratings Power Supply Voltage, (any V PECL Differential Input Voltage............................................................................................ -0. TTL Input Voltage...........................................................................................................................-0.5V to +5.5V TTL Output Voltage .............................................................................................................. -0. TTL Output Current ...................................................................................................................................... 50mA PECL Output Current .................................................................................................................................... 50mA Case Temperature Under Bias, (T Storage Temperature ....................................................................................................... -65 STG Note: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage ...
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... Mutli-Gigabit Interconnect Chip Table 16: Pin Table Page 28 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 G52325-0, Rev. 3.0 6/14/00 ...
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... Preliminary Datasheet VSC7217 Table 17: Pin Description Pin Name I/O 6Y, 8U, 7W, 5Y, I 7V, 7U, TA(7:0) 6W, 5W 11U, 11W, 10Y, 10W, I 10U, 10V, TB(7:0) 9Y, 9W 12A, 11C, 11D, 10A, I 10B, 10D, TC(7:0) 10C, 9A 8D, 8C, 7B, 5A, I 7D, 6B, TD(7:0) 6C C/DA 11V C/DB I 12B C/DC 6A C/DD 8Y WSENA 12Y WSENB I 12C WSENC 8B WSEND 9U TBCA ...
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... Rn(7:0). When ENDEC=LOW, this is equivalent to COMDETn. Kxx.x CHaracter Detect for Channel n. When HIGH, a special Kxx.x TTL character has been detected by the decoder and is on Rn(7:0). When ENDEC=LOW, this is equivalent to data bit Rn8. VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 Pin Description G52325-0, Rev. 3.0 6/14/00 ...
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... Preliminary Datasheet VSC7217 Pin Name I/O 18N ERRA 16U ERRB O 20A ERRC 20F ERRD 20M RCLKA 19M RCLKNA 17T RCLKB 20Y RCLKNB O 18E RCLKC 17E RCLKNC 17K RCLKD 18K RCLKND 6U RMODE0 I 4W RMODE1 1U, 2U PRXA+/- 1Y, 2Y PRXB+/- I 1A, 2A PRXC+/- 1D, 2D PRXD+/- 1W, 2W ...
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... TTL send a 256 byte incrementing data pattern, and all receive channels signal correct reception of the test pattern with a LOW on the TBERRn outputs. ENcoder/DECoder Enable. When HIGH, the VSC7217 is configured for 8 TTL bit operation and internal 8B/10B encoding is enabled. When LOW, a 10-bit interface is used and internal 8B/10B encoding is bypassed ...
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... Preliminary Datasheet VSC7217 Pin Name I/O 11A, 13C, 13U, 19L, 3C, 3K, 3V, VSSD 4C, 4E, 4T, 4V, 6V, 7A, 7C, 8W 14B, 14W, 17B, 17D, 17H, 17P, 17U, 17W, VDDT 18L, 19B, 19E, 19G, 19J, 19N, 19T, 19W 14C, 14V, 16B, 16W, 18C, 18F, 18J, 18M, VSST ...
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... Mutli-Gigabit Interconnect Chip Package Thermal Considerations The VSC7217 is packaged in a 256-pin, 27mm, thermally enhanced BGA in a 20x20 array which offers excellent electrical characteristics, good thermal performance and small size. This package uses an industry- standard footprint. The package construction is shown in Figure 22. ...
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... Preliminary Datasheet VSC7217 Package Information 1.27 Typ 27.0 BOTTOM VIEW G52325-0, Rev. 3.0 6/14/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION 256-pin BGA 1.40 Typ VITESSE SEMICONDUCTOR CORPORATION Multi-Gigabit Interconnect Chip ...
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... Use of a Vitesse product in such applications without the written consent is prohibited. Page 36 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION xx VSC7217 VSC7217UC ####AAAA VITESSE VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 Package UC: 256-Pin, 27mm BGA Package Suffix Lot Tracking Code G52325-0, Rev. 3.0 6/14/00 ...