sta015t-013tr STMicroelectronics, sta015t-013tr Datasheet - Page 28

• Manufacturer Part Number: sta015t-013tr
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

STA015 STA015B STA015T
DRB
Address: 0x49 (73)
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels. Default value
is 0x00, corresponding at the maximum attenuation in the re-direction channel.
CHIP_MODE
Address: 0x4D (77)
Type: R/W
Hardware Reset: 0x00
Using this register it’s possible to select which operation will be performed by the DSP.
Possible values are:
0x00 - MP3 decoding
0x01 - Reserved
0x02 - ADPCM Encoder
0x03 - ADPCM Decoder
0x04 - BYPASS mode
The DSP will check for the value of this register right after the RUN command has been issued (refer to
RUN register). After that no more checks will be performed: therefore a SOFT_RESET must be generated
in order to change the device mode.
CRCR
Address: 0x4E (78)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The CRC register is used to enable/disable the CRC check. If CRC_EN bit is cleared, the CRC value en-
coded in the bitstream is checked against the hardware one. If a discrepance occurs, the current frame is
skipped and the decoder is muted. The ERROR_CODE register is affected with the value 0x01.
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DRB7
MSB
MSB
b7
b7
0
0
0
0
:
X
DRB6
b6
0
0
0
1
:
b6
X
DRB5
b5
0
0
0
1
:
DRB4
b5
X
b4
0
0
0
0
:
DRB3
b3
0
0
0
0
:
b4
X
DRB2
b2
0
0
0
0
:
DRB1
b3
X
b1
0
0
1
0
:
DRB0
LSB
b0
0
1
0
0
:
b2
X
OUTPUT ATTENUATION
NO ATTENUATION
b1
Description
X
-96dB
-1dB
-2dB
:
CRCEN
LSB
b0