sta015t-013tr STMicroelectronics, sta015t-013tr Datasheet - Page 40

• Manufacturer Part Number: sta015t-013tr
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

STA015 STA015B STA015T
Hardware Reset: 0x00
X = don’t care;
0 = no ancillary data
1 = Ancillary Data Available
The ISR is used by the microcontroller to understand when a new ancillary data block is available.
After all ancillary data has been retrieved this bit must be cleared.
ADPCM_CONFIG
Address: 0xB8 (184)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
This register controls ADPCM engine and how data must be compressed.
AFM_EN
ASM_EN:
AA0,AA1:
The above bitrates refers to an 8 KHz 16 bits mono input stream.
Please note that 32KHz stereo mode is only available (both in encoding and decoding) with DVI algorithm
40/55
MSB
MSB
b7
b7
X
X
AA1
0
0
1
1
ADPCM Frame Mode Enable
0 = no frames (raw format)
ADPCM Stereo Mode Enable
0 = Disable stereo mode
1 = Enable stereo mode
ADPCM Algorithm selection The ADPCM encoding/decoding algorithm can be selected
according to the following table:
1 = select the framed output format for ADPCM encoded data
b6
b6
X
X
AA0
b5
b5
0
1
0
1
X
X
DVI algorithm
G723-24 algorithm (24kbp/s)
G721 algorithm (32kbp/s)
G723-40 algorithm (40kbp/s)
b4
b4
X
X
AA1
b3
b3
X
AA0
b2
b2
X
ASM_EN
b1
b1
X
AFM_EN
LSB
LSB
b0
b0
0
1