hmp8117 Intersil Corporation, hmp8117 Datasheet - Page 21

• Manufacturer Part Number: hmp8117
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

In order to perform a read from a specific control register
within the HMP8117, an I
performed to properly setup the address register. Then an
I
control register(s). As a result of needing the write cycle for a
DATA WRITE
DATA READ
2
C bus read can be performed to read from the desired
SDA
SCL
S
S
1000 1000 (R/W)
SDA
SCL
CHIP ADDR
CHIP ADDR
1000 1000
0x88
0x88
CONDITION
START
2
t
S
BUF
C bus write must first be
A
A
21
SUB ADDR
SUB ADDR
ADDRESS
t
LOW
t
SU:DATA
1-7
A
A
FIGURE 19. REGISTER WRITE/READ FLOW
t
t
HD:DATA
HIGH
REGISTER
POINTED
TO BY
SUB ADDR
S
FIGURE 18. I
DATA
FIGURE 17. I
CHIP ADDR
R/W
0x89
8
t
R
A
MAY BE REPEATED
OPTIONAL FRAME
HMP8117
2
C SERIAL DATA FLOW
t
2
DATA
F
ACK
n TIMES
C TIMING DIAGRAM
A
9
REGISTER
POINTED
TO BY
SUB ADDR
DATA
read cycle there are actually two START conditions as
shown in Figure 19. The address register is then
auto-incremented after each byte read during the I
cycle. Reserved registers return a value of
A
P
1-7
A
MAY BE REPEATED
OPTIONAL FRAME
DATA
DATA
n TIMES
FROM MASTER
FROM HMP8117
8
NA
P
ACK
9
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
CONDITION
STOP
P
tSU:STOP
00
H
.
2
April 19, 2007
C read
FN4643.3