hmp8117 Intersil Corporation, hmp8117 Datasheet - Page 39

• Manufacturer Part Number: hmp8117
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

Pin Descriptions
VBIVALID
INTREQ
HSYNC
DVALID
P0-P15
VSYNC
RESET
BLANK
NAME
AGND
CCAP
FIELD
LCAP
CLK2
GND
SDA
VCC
SCL
VAA
PIN
NC
SA
25, 33, 35, 36,
39, 46, 53, 62,
15,16, 21, 22,
26, 31,37, 52,
59, 68, 75, 79
47-51, 54-58,
1, 3, 10, 11,
42, 43, 45,
20, 30, 32,
60, 63, 64
69, 72, 80
73, 74, 77
NUMBER
4, 13, 18,
2, 12, 14
23, 24
PIN
76
29
71
70
67
66
65
61
44
38
34
27
40
41
(Continued)
I/O
I/O
O
O
O
O
O
O
O
O
39
I
I
I
I
I
I
I
I
I
I
0Ω Pulldown
10kΩ Pullup
10kΩ Pullup
10kΩ Pullup
10kΩ Pullup
10kΩ Pullup
10kΩ Pullup
10kΩ Pullup
10kΩ Pullup
4kΩ Pullup
4kΩ Pullup
PASSIVE
to AGND
to AGND
to AGND
0.1µF
0.1µF
0.1µF
none
N/A
or
Storage capacitor for Luminance signal DC restoration. The LCAP voltage offsets the sync
tip to the lower reference of the A/D. A 0.1μF capacitor should be connected between this
pin and AGND. This capacitor should be as close to this pin as possible for best
performance.
Storage capacitor for Chrominance signal DC restoration. The CCAP voltage offsets the
chroma signal to mid-range of the A/D. A 0.1μF capacitor should be connected between
this pin and AGND. This capacitor should be as close to this pin as possible for best
performance.
Pixel output pins. See Table 3. These pins are three-stated after a RESET or software reset.
Horizontal sync output. HSYNC is asserted during the horizontal sync intervals. The
polarity of HSYNC is programmable. This pin is three-stated after a RESET or software
reset and should be pulled high through a 10kΩ resistor.
Vertical sync output. VSYNC is asserted during the vertical sync intervals. The polarity of
VSYNC is programmable. This pin is three-stated after a RESET or software reset and
should be pulled high through a 10kΩ resistor.
FIELD output. The polarity of FIELD is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10kΩ resistor.
Data valid output. DVALID is asserted during CLK2 cycles that contain valid pixel data. This
pin is three-stated after a RESET or software reset and should be pulled high through a
10kΩ resistor.
Composite blanking output. BLANK is asserted during the horizontal and vertical blanking
intervals. The polarity of BLANK is programmable. This pin is three-stated after a RESET
or software reset and should be pulled high through a 10kΩ resistor.
Vertical Blanking Interval Valid output. VBIVALID is asserted during CLK2 cycles that
contain valid VBI (Vertical Blanking Interval) data such as Closed Captioning, Teletext, and
WSS data. The polarity of VBIVALID is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10k resistor.
Interrupt Request Output. This is an open-drain output and requires an external 10kΩ pull-
up resistor to V
2x pixel clock input. This clock must be a continuous, free-running clock. Refer to Table 1
for allowable CLK2 frequencies for each video standard and aspect ratio. For best
performance, use termination resistor(s) to minimize pulse overshoot and reflections.
Reset control input. A logical zero for a minimum of four CLK2 cycles resets the device.
RESET must be a logical one for normal operation.
I
If the SA pin is pulled low, the I
the address is 1000101xB or 8A
I
I
Analog power supply pins. All VAA pins must be connected together.
Analog ground pins. All AGND pins must be connected together. Refer to Applications
section for recommended grounding scheme.
Digital power supply pins. All VCC pins must be connected together.
Digital ground pins. All GND pins must be connected together.
No Connect pins. These pins may be left floating or tied to GND.
2
2
2
C slave address select input. This was formerly the WPE pin on HMP8112/15 decoders.
C data input/output. This pin should be pulled high through a 4kΩ resistor.
C clock input. This pin should be pulled high through a 4kΩ resistor.
HMP8117
CC
.
2
C address is 1000100xB or 88
H
. (The ‘x’ bit is the address is the I2C read flag.)
DESCRIPTION
H
. If the SA pin is pulled high,
April 19, 2007
FN4643.3