sx1511iultrt Semtech Corporation, sx1511iultrt Datasheet - Page 34

• Manufacturer Part Number: sx1511iultrt
• Description: World
• Manufacturer: Semtech Corporation

0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x18
0x19
0x20
ADVANCED COMMUNICATIONS & SENSING
Rev 1 – 24
RegInterruptSourceB
RegInterruptSourceA
RegEventStatusB
RegEventStatusA
RegLevelShifter1
RegLevelShifter2
RegClock
RegMisc
RegLEDDriverEnableB
th
Feb. 2010
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
3:2
1:0
7:0
7:0
7:0
7:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
6:5
3:0
6:4
7:0
7
4
7
3
2
1
0
Edge sensitivity of RegData[1]
Edge sensitivity of RegData[0]
Interrupt source (from IOs set in RegInterruptMask)
0 : No interrupt has been triggered by this IO
1 : An interrupt has been triggered by this IO (an event as configured in relevant
RegSense register occured).
Writing '1' clears the bit in RegInterruptSource and in RegEventStatus
When all bits are cleared, NINT signal goes back high.
Interrupt source (from IOs set in RegInterruptMask)
0 : No interrupt has been triggered by this IO
1 : An interrupt has been triggered by this IO (an event as configured in relevant
RegSense register occured).
Writing '1' clears the bit in RegInterruptSource and in RegEventStatus
When all bits are cleared, NINT signal goes back high.
Event status of all IOs.
0 : No event has occured on this IO
1 : An event has occured on this IO (an edge as configured in relevant RegSense
register occured).
Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant.
If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically
Event status of all IOs.
0 : No event has occured on this IO
1 : An event has occured on this IO (an edge as configured in relevant RegSense
register occured).
Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant.
If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically
Level shifter mode for IO[7] (Bank A) and IO[15] (Bank B)
Level shifter mode for IO[6] (Bank A) and IO[14] (Bank B)
Level shifter mode for IO[5] (Bank A) and IO[13] (Bank B)
Level shifter mode for IO[4] (Bank A) and IO[12] (Bank B)
Level shifter mode for IO[3] (Bank A) and IO[11] (Bank B)
Level shifter mode for IO[2] (Bank A) and IO[10] (Bank B)
Level shifter mode for IO[1] (Bank A) and IO[9] (Bank B)
Level shifter mode for IO[0] (Bank A) and IO[8] (Bank B)
Unused
Oscillator frequency (fOSC) source
00 : OFF. LED driver, keypad engine and debounce features are disabled.
01 : External clock input (OSCIN)
10 : Internal 2MHz oscillator
11 : Reserved
OSCIO pin function (Cf. §4.8)
0 : OSCIO is an input (OSCIN)
1 : OSCIO is an output (OSCOUT)
Frequency of the signal output on OSCOUT pin:
0x0 : 0Hz, permanent "0" logical level (GPO)
0xF : 0Hz, permanent "1" logical level (GPO)
Else : fOSCOUT = fOSC/(2^(RegClock[3:0]-1))
LED Driver mode for Bank B’s fading capable IOs (IO15-12)
0: Linear
1: Logarithmic
Frequency of the LED Driver clock ClkX of all IOs:
0 : OFF. LED driver functionality is disabled for all IOs.
Else : ClkX = fOSC/(2^(RegMisc[6:4]-1))
LED Driver mode for Bank A’s fading capable IOs (IO7-4)
0: Linear
1: Logarithmic
NRESET pin function when externally forced low (Cf. §4.4.1 and §4.9.5)
0: Equivalent to POR
1: Reset PWM/Blink/Fade counters (not user programmed values)
This bit is can only be reset manually or by POR, not by NRESET.
Auto-increment register address (Cf. §4.5)
0: ON. When several consecutive data are read/written, register address is incremented.
1: OFF. When several consecutive data are read/written, register address is kept fixed.
Autoclear NINT on RegData read (Cf. §4.7)
0: ON. RegInterruptSourceA/B is also automatically cleared when RegDataA/B is read.
1: OFF. RegInterruptSourceA/B must be manually cleared, either directly or via
RegEventStatusA/B.
Enables LED Driver for each [output-configured] IO
0 : LED Driver is disabled
1 : LED Driver is enabled
34
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
SX1510/SX1511/SX1512
www.semtech.com
00 : OFF
01 : A->B
10 : B->A
11 : Reserved
00 : OFF
01 : A->B
10 : B->A
11 : Reserved