x96010 Intersil Corporation, x96010 Datasheet
x96010
Available stocks
Related parts for x96010
x96010 Summary of contents
Page 1
... October 25, 2005 DESCRIPTION The X96010 is a highly integrated bias controller which incorporates two digitally controlled Programmable Cur- rent Generators and temperature compensation with dedicated look-up tables. All functions of the device are controlled via a 2-wire digital serial interface. ...
Page 2
... A/D converter and the two D/A converters Current Generator 2 Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits. 2 X96010 Voltage Look-up Mux Table 2 ADC Look-up ...
Page 3
... OHSDA V WP, A0, A1, and A2 input ILCMOS Low voltage 3 X96010 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...
Page 4
... For this range of V(VRef) the full scale sink mode current at I1 and I2 follows V(VRef) with a linearity error smaller than 1%. 4. This parameter is periodically sampled and not 100% tested. 5. TCO = [Max V Min V(V ref REF 4 X96010 (Continued) (Conditions are as follows, unless otherwise specified) Min Typ Max 0.8 x Vcc Vcc 1 ...
Page 5
... V(I1) and V(I2) are V - 1.2V in source mode and 1.2V in sink mode. In this range the current varies <1 The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum V age changes to 2.5V from the sourcing rail, and the current variation is <1%. 5 X96010 Min Typ 1.56 1. ...
Page 6
... DNL errors starting from code 00h to the code where the INL measurement is desired. The measured trans- fer curve is adjusted for Offset and Fullscale errors before calculating INL. 3. These parameters are periodically sampled and not 100% tested. 6 X96010 Min Typ Max ...
Page 7
... WC is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. The minimum frequency requirement applies between a START and a STOP condition. 4. These parameters are periodically sampled and not 100% tested. 7 X96010 Min Typ Max Units ...
Page 8
... Figure 1. Bus Timing t F SCL t SU:DAT t SU:STA t HD:STA SDA IN SDA OUT Figure 2. WP Pin Timing START SCL SDA IN WP Figure 3. Non-Volatile Write Cycle Timing SCL SDA 8th bit of last byte 8 X96010 HIGH LOW R t HD:DAT Clk SU:WP HD:WP ACK Stop Condition t SU:STO ...
Page 9
... The contents of the selected LUT row (8-bit wide) drives the input of an 8-bit D/A converter, which gener- ates the output current. All control and setup parameters of the X96010, including the look-up tables, are programmable via the 2-wire serial port. Look Up ...
Page 10
... When the NV1234 bit is set to “0” (default), bytes writ- ten to Control registers and 4 are stored in vol- atile cells, and their content is lost when the X96010 is powered down. When the NV1234 bit is set to “1”, bytes written to Control registers and 4 are stored in both volatile and nonvolatile cells, and their value doesn’ ...
Page 11
... Write Disabled 1: Write Enabled ADC Output 87h AD7 AD6 Volatile Registers in byte addresses 88h through 8Fh are reserved. Register bits shown should always use those values for proper operation. 11 X96010 NV1234 ADCfiltOff 1 VRM Control ADC Voltage filtering ...
Page 12
... The I2DS bit sets the polarity of Current Generator 2, DAC2. When this bit is set to “0” (default), the Current Generator 2 of the X96010 is configured as a Current Source. Current Generator 2 is configured as a Cur- rent Sink when the I2DS bit is set to “1”. See Figure 7. ...
Page 13
... ATCH OLATILE The WEL bit controls the Write Enable status of the entire X96010 device. This bit must be set to “1” before any other Write operation (volatile or nonvolatile). Oth- erwise, any proceeding Write operation to memory is aborted and no ACK is issued after a Data Byte. ...
Page 14
... VOLTAGE REFERENCE The voltage reference to the A/D and D/A converters on the X96010, may be driven from the on-chip volt- age reference, or from an external source via the VRef pin. Bit VRM in Control Register 0 selects between the two options (See Figure 5). The default value of VRM is “0”, which selects the internal reference. When the internal reference is selected, it’ ...
Page 15
... External VSense Pin All voltages referred to Vss. LOOK-UP TABLES The X96010 memory array contains two 64-byte look- up tables. One is associated to pin I1’s output current generator and the other to pin I2’s output current gen- erator, through their corresponding D/A converters. The output of each look-up table is the byte contained in the selected row ...
Page 16
... Figure 7. D/A Converter Block Diagram VRef Voltage DAC1 or Divider DAC2 Input byte Figure 8. Look-up Table (LUT) Operation LUT2 Row Selection bits D0h LUT1 Row Selection bits 90h 16 X96010 Vcc Polarity I1DS or I2DS: bits Control Select register 0. Circuit + - D2DA[7:0] : Control register 4 LUT2 10Fh 6 A ...
Page 17
... The full scale output current has a maximum value of ±3.2 mA, which is obtained using a resistance of 255Ω for Rx. This resistance is con- nected externally to pin Rx of the X96010. Bits I1DS and I2DS in Control Register 0 select the direction of the currents through pins I1 and I2 inde- pendently (See “ ...
Page 18
... See Figure 7, and the descriptions of the control bits. 18 X96010 POWER-ON RESET When power is applied to the Vcc pin of the X96010, the device undergoes a strict sequence of events before the current outputs of the D/A converters are enabled. When the voltage at Vcc becomes larger than the power-on reset threshold voltage (V recalls all control bits from non-volatile memory into volatile registers ...
Page 19
... Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP condi- tions. See Figure 12. On power-up of the X96010, the SDA pin is in the input mode. Serial Start Condition ...
Page 20
... SDA Figure 12. Valid Data Changes on the SDA Bus SCL SDA Figure 13. Acknowledge Response From Receiver SCL from Master SDA Output from Transmitter SDA Output from Receiver START 20 X96010 START Data Stable Data Change 1 STOP Data Stable 8 9 ACK October 25, 2005 FN8214.1 ...
Page 21
... Addressing Protocol Overview All Serial Interface operations must begin with a START, followed by a Slave Address Byte. The Slave address selects the X96010, and specifies if a Read or Write operation performed. It should be noted that the Write Enable Latch (WEL) bit must first be set in order to perform a Write opera- tion to any other bit. (See “ ...
Page 22
... Issue STOP responds with an ACK. The master then terminates the transfer by generating a STOP condition. At this time, if all data bits are volatile, the X96010 is ready for the next read or write operation. If some bits are non- volatile, the X96010 begins the internal write cycle to NO the nonvolatile memory ...
Page 23
... Figure 18). After the receipt of each byte, the X96010 responds with an ACK, and the internal byte address counter is incremented by one. The page address remains constant. When the counter reaches the end of the page, it “ ...
Page 24
... START, the Slave Address byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Slave Address byte with the R/W bit set to “1”. After each of the three bytes, the X96010 responds with an ACK. Then the X96010 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eigth bit of each byte ...
Page 25
... K K Data Protection There are three levels of data protection designed into the X96010: 1- Any Write to the device first requires setting of the WEL bit in Control 6 register; 2- The Write Protection pin disables any writing to the X96010; 3- The proper clock count, data bit sequence, ...
Page 26
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 26 X96010 14-Lead Plastic, TSSOP, Package Code V14 .025 (.65) BSC .169 (4.3) ...