qt1060 Quantum Research Group, qt1060 Datasheet - Page 12

• Manufacturer Part Number: qt1060
• Description: Qtouch? 6-channel Sensor Ic
• Manufacturer: Quantum Research Group

4.3.2
12
AT42QT1060
Reading Data From the Device
Table 4-1.
Note: the host should not try to write beyond address 255 because this is the limit of the device’s
internal memory address.
The sequence of events required to read data from the device is shown next.
Key
MemAddress
Data
P
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to write to.
5. The device sends an ACK.
6. The host transmits one or more data bytes; each is acknowledged by the device.
7. If the host sends more than one data byte, they are written to consecutive memory
8. The device automatically increments the target memory address after writing each data
9. After writing the last data byte, the host should send the STOP condition.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to read from.
5. The device sends an ACK.
6. The host must then send a STOP and a START condition followed by the slave address
7. The device returns an ACK, followed by a data byte.
8. The host must return either an ACK or NACK.
WRITE bit.
addresses.
byte.
WRITE bit.
again but this time accompanied by the READ bit.
a. If the host returns an ACK, the device subsequently transmits the data byte from
b. If the host returns a NACK, it should then terminate the transfer by issuing the
the next address. Each time a data byte is transmitted, the device automatically
increments the internal address. The device continues to return data bytes until the
host responds with a NACK.
STOP condition.
Description of Write Data Bits
S
SLA+W
Data 1
A
A
Host to Device
MemAddress
Data 2
Description
Target memory address within device
Data to be written
Stop condition
A
A
P
S
Device to Host
SLA+R
Data n
A
/A
P
9505D–AT42–12/08