lm25117psqx National Semiconductor Corporation, lm25117psqx Datasheet - Page 19

• Manufacturer Part Number: lm25117psqx
• Description: Wide Input Range Synchronous Buck Controller With Analog Current Monitor
• Manufacturer: National Semiconductor Corporation

SUB-HARMONIC OSCILLATION
Peak current mode regulators can exhibit unstable behavior
when operating above 50% duty cycle. This behavior is
known as sub-harmonic oscillation and is characterized by
alternating wide and narrow pulses at the SW pin. Sub-har-
monic oscillation can be prevented by adding an additional
voltage ramp (slope compensation) on top of the sensed in-
ductor current shown in
regulator will not be subject to sub-harmonic oscillation
caused by a varying input voltage.
In time-domain analysis, the steady-state inductor current
starts and ends at the same value during one clock cycle. If
the magnitude of the end-of-cycle current error, dI
by an initial perturbation, dI
dI
a few cycles. When dI
not disappear, resulting in sub-harmonic oscillation in steady-
state operation.
FIGURE 16. Effect of Initial Perturbation when dl
dI
The relationship between dI
graphically in
The minimum value of K is 0.5. When K<0.5, the amplitude
of dI
0
1
/dI
or dI
1
0
is greater than the amplitude of dI
can be calculated by:
1
/dI
0
> -1, the perturbation naturally disappears after
Figure
FIGURE 17. dl
17.
1
/dI
0
Figure
< -1, the initial perturbation does
0
1
, is less than the magnitude of
1
/dI
/dl
0
0
7. By choosing K
vs K Factor
and K factor is illustrated
0
and any initial per-
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1
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1
, caused
/dl
≥
1, the
0
(19)
< -1
19
turbation results in sub-harmonic oscillation. If K=1, any initial
perturbation will be removed in one switching cycle. This is
known as one-cycle damping. When -1<dl
perturbation will be under-damped. Any perturbation will be
over-damped when 0<dl
In the frequency-domain, Q, the quality factor of the sampling
gain term in the modulator transfer function, is used to predict
the tendency for sub-harmonic oscillation, which is defined
as:
The relationship between Q and K factor is illustrated graph-
ically in
The minimum value of K is 0.5 again. This is the same as time
domain analysis result. When K<0.5, the regulator is unsta-
ble. High gain peaking at 0.5 results in sub-harmonic oscilla-
tion at F
equal to 0.673 at this point. A higher K factor may introduce
additional phase shift by moving the sampled gain inductor
pole closer to the crossover frequency, but will help reduce
noise sensitivity in the current loop. The maximum allowable
value of K factor can be calculated by the Maximum
Crossover Frequency equation in
PC BOARD LAYOUT RECOMMENDATION
In a buck regulator the primary switching loop consists of the
input capacitor, NMOS power switches and current sense re-
sistor. Minimizing the area of this loop reduces the stray
inductance and minimizes noise and possible erratic opera-
tion. High quality input capacitors should be placed as close
as possible to the NMOS power switches, with the V
the capacitor connected directly to the high-side NMOS drain
and the ground side of the capacitor connected as close as
possible to the current sense resistor ground connection.
Connect all of the low power ground connections (R
R
AGND pin. Connect C
Note that C
sible to the IC. AGND and PGND must be directly connected
together through a top-side copper pattern connected to the
exposed pad. Ensure no high current flows beneath the un-
derside exposed pad.
FB1
, C
SS
Figure
SW
FIGURE 18. Sampling gain Q vs K Factor
, C
/2. When K=1, one-cycle damping is realized. Q is
VIN
RES
and C
18.
, C
CM
VCC
, C
VCC
1
VIN
must be as physically close as pos-
/dl
directly to the regulator PGND pin.
, C
0
<1.
RAMP
Table
) directly to the regulator
1.
1
/dl
0
<0, any initial
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IN
UV1
side of
, R
(20)
T
,