ncn6804 ON Semiconductor, ncn6804 Datasheet - Page 22

• Manufacturer Part Number: ncn6804
• Description: Dual Smart Card Interface Ic With Spi Programming Interface
• Manufacturer: ON Semiconductor

over current exist over the full temperature range. As a
matter of fact, the output current limit is reduced when the
temperature increases.
DC-T O-DC Converter External PASSIF Component
Selection
need external passive components carefully selected. The
performance and specification compliance of the NCN6804
are guaranteed by the DC/DC converter input capacitor, by
the inductor and the reservoir capacitor characteristics. The
input capacitor enables the decoupling and filtering of the
input power supply voltage (V
high enough to guarantee a good operating stability of the
converter. A CMS very low ESR capacitor shall be
preferably used with a minimum value of 4.7 mF
recommended, 10 mF will be preferred - this will strongly
depend on how the capacitance value varies with the DC
voltage applied across the capacitor terminals (see
Figure 21). The inductor shall be sized to handle the 500 mA
peak current (Min. I
and will have to offer a low parasitic series resistor in order
to
1008PS-223KLC). The reservoir output capacitor shall be
also ceramic surface mount capacitor with very low ESR
(lower than 50 mW) and good temperature characteristics
(X7R type). 10 mF is the recommended capacitance value
under 5 V, 3 V and 1.8 V to get the better operating
performance with a low CRD_VCC ripple level. The CMS
capacitor shall be selected accordingly that is with a
capacitance value of 10 mF covering the range 1.8 V – 5 V
(see Figure 21). This value constitutes a good compromise
for a good CRD_VCC ripple and CRD_VCC turn-on and
turn-of f times.
On the other hand, the circuit is designed to make sure no
To be functional the NCN6804's DC-to-DC converters
Figure 20. Output Current Limit: Output voltage
6
5
4
3
2
1
0
maintain
0
CRD_VCC (1.8 V, 3.0 V, 5.0 V)
a
sat
50
good
) flowing during the DC/DC operation
ICRD_VCC (mA)
1.8 V
efficiency
3.0 V
BAT
100
) and its value has to be
5.0 V
(Ex:
150
Coilcraft,
http://onsemi.com
200
NCN6804
22
Smart Card Clock Divider
folds:
the mC to get the Duty Cycle window as defined by the
ISO7816-3 specification.
programming functions when CS is Low as depicted
Figures 22 and 23. The clock input stage (CLOCK_IN) can
handle a 40 MHz frequency maximum signal, the divider
being capable to provide a 1:4 ratio. Of course, the ratio
must be defined by the engineer to cope with the Smart Card
considered in a given application and, in any case, the output
clock [CRD_CLKA/B] shall be limited to 20 MHz
maximum. In order to minimize the dI/dt and dV/dV
developed in the CRD_CLKA/B line, the output stage
includes a special function to adapt the slope of the clock
signal for different applications. This function is
programmed by the MOSI register (see Table 2) whatever be
the clock division.
1.2E+7
1E+7
8E+6
6E+6
4E+6
2E+6
The main purpose of the built in clock generator is three
In addition, the NCN6804 adjusts the signal coming from
The byte content of the SPI port b2 and b3 fulfills the
Figure 21. Variation of the Capacitance Value of
Different CMS Capacitors with the DC Voltage
1. Adapts the voltage level shifter to cope with the
2. Provides a frequency division to adapt the Smart
3. Controls the clock state according to the smart
0
different voltages that might exist between the
MPU and the Smart Card
Card operating frequency from the external clock
source.
card specification.
Applied Across its Terminals
10 mF, Y5V, 0805, 16 V
1.25
DC BIAS VOLTAGE (V)
2.5
10 mF, X5R, 1206, 16 V
10 mF, X7R, 1210, 16 V
3.75
10 mF, X7R,
0805, 10 V
5
6.25