ncn6804 ON Semiconductor, ncn6804 Datasheet - Page 23

• Manufacturer Part Number: ncn6804
• Description: Dual Smart Card Interface Ic With Spi Programming Interface
• Manufacturer: ON Semiconductor

upon the specific application, prior to be applied to the smart
card driver. On the other hand, the positive and negative
going slopes of the output clock (CRD_CLKA/B) can be
programmed to optimize the operation of the chip: see
Table 9. Output Clock Rise and Fall Time Selection
The input clock can be divided by 1/1, ½, or ¼,, depending
CLOCK_IN
CLOCK : 1
CLOCK : 2
CLOCK : 4
Figure 22. Typical Clock Divider Synchronization
CRD_CLK
B0
0
0
1
1
VCC
CLK_IN
SYNC
B2
B0
B1
B3
B2
B3
B1
0
1
0
1
Programming
CRD_CLK
Division
CLOCK programming is activated
by the B2 + B3 logic state
Division Ratio
CRD_CLK
1/2
1/4
-
1
Figure 23. Basic Clock Divider and Level Shifter
Clock is updated upon
CLOCK: 4 rising edge
These bits program
CLOCK = 1:1 ratio
CRD_CLK Slope
Programming
ASYNC
SYNC
Internal
CLOCK
Divider
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B
A
Output Clock = Low
NCN6804
SEL
10 ns (typ.)
10 ns (typ.)
10 ns (typ.)
CRD_CLK
SLO_SLP
23
DIGITAL_MUX
OUT
NOTE: Bits [B0...B3] come from SPI data
ISO7816-3 specification, the divider is synchronized by the
last flip flop, thus yielding a constant 50% duty cycle,
whatever be the divider ratio (see Figure 22). Consequently,
the output CRD_CLKA/B frequency division can be
delayed by four CLOCK_IN pulses and the micro controller
software must take this delay into account prior to launch a
new data transaction. On the other hand, the output signal
Duty Cycle cannot be guaranteed 50% if the division ratio
is 1 and if the input Duty Cycle signal is not within the 46%
– 56% range.
automatically routed to the level shifter and control block
according to the mode of operation.
Table 2. The slope of the output clock can be programmed
on the fly, independently of either the CRD_VCCA/B
voltage or the operating frequency, but cares must be
observed as the CRD_RSTA/B will reflect the logic state
present at MOSI / b4 register.
U1
In order to avoid any duty cycle out of the smart card
The input signals CLK_IN and MOSI/b3 are
LEVEL SHIFTER
AND CONTROL
Output Clock = Low
CRD_CLK
FST_SLP
2 ns (typ.)
2 ns (typ.)
2 ns (typ.)
CRD_CLK
CRD_VCC