tc5299j ETC-unknow, tc5299j Datasheet - Page 22

• Manufacturer Part Number: tc5299j
• Description: Fast Ethernet Pcmcia Controller
• Manufacturer: ETC-unknow

Note: Following coding applies to CRC and FAE bits
FAE
0
0
1
1
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Bit
D0
D1
D2
D3
D4
D5
5.7.7
CRC
0
1
0
1
Interrupt Mask Register (IMR)
Symbol
PRX
CRC
FAE
FO
MPA
PHY
DIS
DFR
Symbol
PRXE
PTXE
RXEE
TXEE
OVWE
CNTE
The interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in
the Interrupt Status Register (ISR). If an interrupt mask bit is set, an interrupt will be issued whenever
the corresponding bit in the ISR is set. If any bit in the IMR is set low, an interrupt will not occur when
the bit in the ISR is set. The IMR powers up all zeroes.
DFR
7
-
Type of Error
No error (Good CRC and <6 Dribble Bits)
CRC ERROR
Legal, will not occur
Frame Alignment Error and CRC Error
RDCE
DIS
Description
Packet Received Intact: Indicates packet received without error. (Bits CRC, FAE,
FO and MPA are zero for the received packet.)
CRC Error: Indicates packet received with CRC error. Increments Tally Counter
(CNTR1). This bit will also be set for Frame Alignment errors.
Frame Alignment Error: Indicates that the incoming packet did not end on a byte
boundary and the CRC did not match at last byte boundary. Increments Tally
counter (CNTR0).
FIFO Overrun: This bit is set when the FIFO is not serviced causing overflow
during reception. Reception of the packet will be aborted.
Missed Packet: Set when packet intended for node cannot be accepted by TC5299J
because of a lack of receive buffers of if the controller is in monitor mode and did
not buffer the packet to memory. Increments Tally Counter (CNTR2).
Physical/Multicast Address: Indicates whether received packet had a physical or
multicast address type
0: Physical Address Match
1: Multicast/Broadcast Address Match
Receiver Disabled: Set when receiver disabled by entering Monitor mode. Reset
when receiver is re-enabled when exiting Monitor mode.
Deferring: Set when CRS or COL inputs are active. If the transceiver has asserted
the CD line as a result of the jabber, this bit will stay set indicating the jabber
condition.
Description
Packet Received Interrupt Enable: Enables Interrupt when packet received.
Packet Transmitted Interrupt Enable: Enables Interrupt when packet is transmitted.
Receive Error Interrupt Enable: Enables Interrupt when packet received with error.
Transmit Error Interrupt Enable: Enables Interrupt when packet transmission
results in error.
Over Write Warning Interrupt Enable: Enables Interrupt when Buffer management
Logic lacks sufficient buffers to store incoming packet.
Counter Overflow Interrupt Enable: Enables Interrupt when MSB of one or more
6
f h N
CNTE
PHY
5
k T ll
OVWE
MPA
4
-22-
TXEE
h
FO
3
b
0FH(Write)
RXEE
FAE
2
PTXE
CRC
1
PRXE
PRX
0
07/04/01
Ver. 0.1
TC5299J