tc5299j ETC-unknow, tc5299j Datasheet - Page 8

• Manufacturer Part Number: tc5299j
• Description: Fast Ethernet Pcmcia Controller
• Manufacturer: ETC-unknow

3.3 Power On Configuration
Figure 1 shows how the RESET circuitry operates.
The TC5299J Controller use a 93C56/66 EEPROM, The programmed contents of the EEPROM is shown as
following.
The TC5299J Controller configures itself after a RST signal is applied. When a Power-On-Reset occurs the
TC5299J controller latches up the values on the configuration pins and uses these to configure the internal registers
and options. Internally these pins contain pull-up resistance. If pins are unconnected they have default logic. The
configuration registers are loaded JMP0 & JMP1 setting when RST goes inactive.
A Power-On-Reset also causes the Controller to load the internal PROM from the EEPROM, which can take up to
3 ms. This occurs after “Config-Regs.” has completed. If EECONFIG is high the configuration data loaded on the
falling edge of RST will be overwritten with data read from the serial EEPROM. Regardless of the level on
EECONFIG the PROM store will always be loaded with data from the serial EEPROM during the time specified
as EELOAD.
0FH
0EH
13H
12H
11H
10H
08H
07H
04H
03H
02H
01H
00H
:::::
:::::
E E l o a d
R E S E T
Regload
V C C
D15
E
net Address 5
E
net Address 3
E
net Address 1
EEPROM Programming Map
CIS byte n
CIS byte 3
CIS byte 1
Config. B
Not Used
Reserved
Reserved
Reserved
Reserved
........
........
42H
57H
-8-
D8 D7
bit [0]: 8-bit enable
bit [7:1]: Reserved
E
net Address 4
E
net Address 2
E
net Address 0
CIS byte n-1
CIS byte 2
CIS byte 0
Config. A
Reserved
Reserved
Reserved
Config C
........
........
42H
57H
D0
07/04/01
Ver. 0.1
TC5299J