w83977ctf Winbond Electronics Corp America, w83977ctf Datasheet - Page 5

• Manufacturer Part Number: w83977ctf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

4.3 DEMODULATION BLOCK DIAGRAM ........................................................................................ 62
5.0 PARALLEL PORT .............................................................................................63
5.1 PRINTER INTERFACE LOGIC .................................................................................................. 63
5.2 ENHANCED PARALLEL PORT (EPP) ....................................................................................... 64
5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .............................................................. 69
4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ................................................. 58
4.2.8 Bank0.Reg7 - User Defined Register (UDR/AUDR).............................................................. 59
4.2.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ........................................................... 60
4.2.10 Bank1.Reg2 - Version ID Regiister I (VID) .......................................................................... 61
4.2.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) .... 61
4.2.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)................................................................. 61
4.2.13 Bank1.Reg5 - Timer High Byte Register (TMRH) ............................................................... 61
5.2.1 Data Swapper..................................................................................................................... 65
5.2.2 Printer Status Buffer ............................................................................................................ 65
5.2.3 Printer Control Latch and Printer Control Swapper .............................................................. 66
5.2.4 EPP Address Port................................................................................................................ 66
5.2.5 EPP Data Port 0-3 ............................................................................................................... 67
5.2.6 Bit Map of Parallel Port and EPP Registers.......................................................................... 67
5.2.7 EPP Pin Descriptions.......................................................................................................... 68
5.2.8 EPP Operation..................................................................................................................... 68
5.3.1 ECP Register and Mode Definitions ..................................................................................... 69
5.3.2 Data and ecpAFifo Port........................................................................................................ 70
5.3.3 Device Status Register (DSR)............................................................................................. 70
5.3.4 Device Control Register (DCR) ............................................................................................ 71
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ....................................................................... 72
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................... 72
5.3.7 tFifo (Test FIFO Mode) Mode = 110.................................................................................... 72
5.3.8 cnfgA (Configuration Register A) Mode = 111 ..................................................................... 72
5.3.9 cnfgB (Configuration Register B) Mode = 111 .................................................................... 72
5.3.10 ecr (Extended Control Register) Mode = all ....................................................................... 73
-III -
Publication Release Date: March 1999
W83977EF/ CTF
PRELIMINARY
Revision A1