sak-xc167ci-32f40f-bb-a Infineon Technologies Corporation, sak-xc167ci-32f40f-bb-a Datasheet - Page 28

• Manufacturer Part Number: sak-xc167ci-32f40f-bb-a
• Description: 16-bit Single-chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

3.3
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Figure 4
Based on these hardware provisions, most of the XC167’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift
Data Sheet
CPU
M AC
P refetch
M u ltip ly
B ranch
FIFO
ID X 0
ID X 1
M A H
Q X 0
Q X 1
U nit
U nit
U nit
+ /-
+ /-
Central Processing Unit (CPU)
CPU Block Diagram
C S P
C P U C O N 1
C P U C O N 2
R etu rn
M R W
M C W
M S W
M A L
S tack
Q R 0
Q R 1
+ /-
IP
IFU
D ivisio n U n it
M u ltip ly U n it
ZE R O S
D P P 0
D P P 1
D P P 2
D P P 3
P S W
M D C
M D H
Exception
Injection/
V E C S E G
Handler
B it-M a sk-G e n .
TF R
B a rre l-S h ifte r
26
S P S E G
S T K O V
S T K U N
O N E S
M D L
S P
+ /-
ADU
ALU
RF
DM U
PM U
G P R s
2-S tage
R 15
R 14
5-S tage
G P R s
R 1
R 0
B uffer
R 15
R 14
P refetch
R 1
R 0
P ipeline
C P
G P R s
P ipeline
R 15
R 14
R 1
R 0
IPIP
W B
Functional Description
Peripherals
Flash/RO M
XC167CI-16F
m ca04917_x.vsd
DPRAM
DSRAM
PSRAM
Derivatives
V1.3, 2006-08
EBC
G P R s
R 1 5
R 1 4
R 1
R 0