sak-xc167ci-32f40f-bb-a Infineon Technologies Corporation, sak-xc167ci-32f40f-bb-a Datasheet - Page 70
sak-xc167ci-32f40f-bb-a
Manufacturer Part Number
sak-xc167ci-32f40f-bb-a
Description
16-bit Single-chip Microcontroller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.SAK-XC167CI-32F40F-BB-A.pdf
(90 pages)
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4.4
4.4.1
The internal operation of the XC167 is controlled by the internal master clock
The master clock signal
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
This influence must be regarded when calculating the timings for the XC167.
Figure 15
Note: The example for PLL operation shown in
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
same frequency as the master clock (
two:
Data Sheet
f
CPU
the example for prescaler operation refers to a divider factor of 2:1.
Phase Locked Loop Operation (1:N)
f
f
Direct Clock Drive (1:1)
f
f
Prescaler Operation (N:1)
f
f
OSC
MC
OSC
MC
OSC
MC
=
f
AC Parameters
Definition of Internal Timing
MC
Generation Mechanisms for the Master Clock
/ 2. This factor is selected by bit CPSYS in register SYSCON1.
f
MC
can be generated from the oscillator clock signal
f
CPU
68
=
f
MC
) or can be the master clock divided by
Figure 15
f
CPU
. The CPU clock can have the
refers to a PLL factor of 1:4,
TCM
Electrical Parameters
TCM
TCM
MCT05555
XC167CI-16F
Derivatives
V1.3, 2006-08
f
MC
f
OSC
.
f
MC
via
.
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