stccp27 STMicroelectronics, stccp27 Datasheet
stccp27
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stccp27 Summary of contents
Page 1
... L =1.8V Two dedicated I L bidirectional controls from camera and µC devices. The STCCP27 is offered in a µTFBGA package to optimize PCB space. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity from transient excess voltage. The STCCP27 is characterized for operation over the commercial temperature range -40° ...
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... STCCP27 Figure 1: Simplified Application Block Diagram Figure 2: Block Diagram 2 Figure 3: Simplified I C Line Block Diagram 2/15 ...
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... Receivers Enable Input CLK Clock Output H-SYNC Horizontal Sync Output V-SYNC Vertical Sync Output GND Ground V Main Supply Voltage DD Sync Sel Select Sync Input V Secondary Supply Voltage L 2 I Line (V VL1 VL2 2 I/O I Line (V VDD1, VDD2 STCCP27 NAME AND FUNCTION Referred) L Referred) DD 3/15 ...
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... STCCP27 Table 3: Main Function Table INPUT ENABLE SYNC_SEL SOF ( EOF( SOL( EOL( High Impedance Low Voltage Level High Voltage Level Don’t care 2 Table Bus Function Table ENABLE Open: If I/O is not driven then the I/O ...
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... VL Parameter ) VDD ) VL , I/O ; 10% to 90%; 90% to VDD VL Value -0.5 to 4.6 -0.5 to 4.6 -0.5 to 4.6 -0.5 to 4.6 -0.5 to 4 0.5) VDD DD -0 0.5) L -65 to +150 ±2 Min. Typ. Max. 2.65 2.8 3.6 1.65 1.8 1.95 0.1 0.4 0.5 0.9 1.3 3 100 120 10 -40 85 -40 125 10 STCCP27 Unit °C KV Unit Ω pF °C °C ns 5/15 ...
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... STCCP27 Table 7: Electrical Characteristics (Over recommended operating conditions unless otherwise noted. All typical values are 25°C, and V A Symbol Parameter V Common Mode Input CM Voltage (See fig.1) V Receiver Input Low THL Threshold V Receiver Input High THH Threshold I Input Leakage Current I (D+, D-, CLK1+, CLK1-) ...
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... V = 0.9V 150mV CM D,CLK D D,CLK = 25°C and V = 2.8V Min. Typ. Max. 3.1 2.0 6.5 6.5 6.5 6.5 1000 1 2.4 1000 0.6 1.0 STCCP27 = 1.8V) Unit 4 8.5 ns 8.5 ns 8 µ 416 MHz 7/15 ...
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... STCCP27 Table 9: Capacitive Characteristics Symbol Parameter Input Capacitance C IN (SYNC_SEL, EN) Figure (Differential Input Signals D+,D- and CLK+,CLK-) SUD-CLK , HCLK-D Figure 7: Bit order in synchronization codes and data, LSB first (example Start of Frame), Image Frame Structure Note: LSB (bytewise Least Significant Bit first) ...
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... TIMING DIAGRAM (unless otherwise specified T Figure 8: DISABLED SYNC MODE Free Running Clock IN (SYNC_SEL=GND) (D1-D8 will get out input data DIN, including Sync Code) = 25°C) A STCCP27 9/15 ...
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... STCCP27 Figure 9: ENABLED SYNC MODE Free Running Clock IN (SYNC_SEL=V input data DIN only, excluding Sync Code) 10/15 ) (D1-D8 will get out DD ...
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... Figure 10: ENABLED SYNC MODE Gated Clock IN (SYNC_SEL=VDD) (D1-D8 will get out input data DIN only, excluding Sync Code) STCCP27 11/15 ...
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... STCCP27 Figure 11: ENABLED SYNC MODE Free Running Clock IN (SYNC_SEL=V input data DIN only, excluding Sync Code Figure 12: DISABLED SYNC MODE Free Running Clock IN (SYNC_SEL=Gnd) (D1-D8 will get out input data DIN only, excluding Sync Code) 12/15 ) (D1-D8 will get out DD ...
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... MECHANICAL DATA DIM. MIN 0.78 b 0. mm. TYP MAX. 1.1 1.16 0.25 0.86 0.30 0.35 3.0 3.1 114.2 2 3.0 3.1 114.2 2 0.5 0.25 STCCP27 mils MIN. TYP. 39.4 43.3 30.7 9.8 11.8 118.1 78.8 118.1 78.8 19.7 9.8 7539979/A MAX. 45.7 9.8 33.9 13.8 122.0 122.0 13/15 ...
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... STCCP27 Table 10: Revision History Date Revision 31-Jan-2005 1 14/15 Description of Changes First Release. ...
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