sta538 STMicroelectronics, sta538 Datasheet - Page 44

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sta538

Manufacturer Part Number
sta538
Description
2 X 1.3 W Class-d Amplifier With Analog Or Digital Input 2.0 Multichannel Digital Audio Processor With Ffx
Manufacturer
STMicroelectronics
Datasheet
Registers
P2SCFG0
Address:
Type:
Buffer:
Reset:
Description:
44/59
BICLK_ STRB
Bit 7
LRCLK_LEFT
3:1 DATA_FORMAT[2:0]: serial interface protocol format:
7 BICLK_STRB: defines the bit clock edges:
6 LRCLK_LEFT: defines the channel for the LR clock:
5 SDATAO_ ACT: sets the behavior of pin SDATAO:
4 MSB_FIRST: data alignment in the protocol for SDATAI and SDATAO:
0 MASTER_ MODE: selects serial interface master/slave mode:
Bit 6
0: strobe is falling edge, active edge is rising
1: strobe is rising edge, active edge is falling (default)
0: clock is low for left channel, high for right channel
1: clock is high for left channel, low for right channel (default)
0: output is tri-stated when no data is sent (default)
1: output is never in tri-state (it is 0 when no data is sent)
0: LSB is the first bit
1: MSB is the first bit (default)
000: left justified
001: I
010: right justified
100: PCM no delay
101: PCM delay
111: DSP
0: slave
1: master (default)
0x0C
R/W
No
0xD3
2
S (default)
SDATAO_ACT
Bit 5
Parallel-to-serial audio interface configuration
register 0
MSB_FIRST
Bit 4
Bit 3
DATA_FORMAT[2:0]
Bit 2
Bit 1
MASTER_
MODE
STA538
Bit 0

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