lm4934rlx National Semiconductor Corporation, lm4934rlx Datasheet - Page 22

• Manufacturer Part Number: lm4934rlx
• Description: 3d Audio Sub-system With Stereo Speaker, Ocl/se Stereo Headphone, Earpiece And Mono Line Level Outputs
• Manufacturer: National Semiconductor Corporation

www.national.com
Further Notes on PLL Programming
Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used).
Remembering that the P divider can divide by half integers. So for P = 4.0 → 7.0 sweep the M inputs from 2.5 → 24. The most
accurate N and N_MOD can be calculated by:
N = FLOOR(((Fout/Fin)*(P*M)),1)
N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0)
This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a VCO frequency
of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which gives a sample rate of
44.099985443kHz, or accurate to 0.33 ppm.
Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used in the above
mode. The I2S should be master on the LM4934 so that the data source can support appropriate SRC as required. This method
should only be used with data being read on demand to eliminate sample rate mismatch problems.
Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this rather than the PLL.
The LM4934 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock without the use of the PLL. This saves
power and reduces clock jitter.
Clock Configuration Register
This register is used to control the multiplexers and clock R divider in the clock module.
CLOCK (09h) (Set = logic 1, Clear = logic 0)
Bits
7:4
0
1
2
3
AUDIO_CLK_SEL
FAST_CLOCK
PLL_ENABLE
PLL_INPUT
Register
R_DIV
DAC_CLK_SEL
FAST_CLOCK
Selects which clock is passed to the audio sub-system
PLL_INPUT
22
(Continued)
R_DIV
Programs the PLL input multiplexer to select:
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
If set enables the PLL. (MODES 4–7 only)
0
1
0
1
0
1
If set master clock is divided by two.
Programs the R divider
Description
MCLK Frequency
PLL Input Source
DAC Sub-system
I2S Input Clock
Input Source
Divide Value
Divided by 2
PLL Output
PLL Input
Normal
MCLK
1.5
2.5
3.5
4.5
5.5
6.5
7.5
1
1
2
3
4
5
6
7
8