lm4934rlx National Semiconductor Corporation, lm4934rlx Datasheet - Page 25

• Manufacturer Part Number: lm4934rlx
• Description: 3d Audio Sub-system With Stereo Speaker, Ocl/se Stereo Headphone, Earpiece And Mono Line Level Outputs
• Manufacturer: National Semiconductor Corporation

Interface Control Register
This register is used to control the I2S and I
INTERFACE (0Fh) (Set = logic 1, Clear = logic 0)
NOTES:
The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample rate). The duty cycle is 40/60.
In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLTION and the duty cycle is always 50-50. In slave mode it will decode any I2S
compatible data stream.
Bits
0
1
2
3
2
Register
I2S_MASTER_SLAVE
I2S_RESOLUTION
I2S_MODE
I2C_FAST
C compatible interface on the chip.
I2S Mode Timing
25
Description
If set the LM4934 acts as a master
for I2S, so both I2S clock and I2S
word select are configured as
outputs. If cleared the LM4934 acts
as a slave where both I2S clock and
word select are configured as inputs.
If set the I2S resolution is set to 32
bits. If clear, resolution is set to 16
bits. This bit only affects the I2S
Interface in master mode. In slave
mode the I2S Interface can support
any I2S compatible resolution. In
master mode the I2S resolution also
depends on the DAC mode as the
note below explains.
If set the I2S is configured in left
justified mode timing. If clear, the
I2S interface is configured in normal
I2S mode timing.
If set enables the I2C to run in fast
mode with an I2C clock up to
3.4MHz. If clear the I2C speed gets
its default value of a maximum of
400kHz
201669A9
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