lm4934rlx National Semiconductor Corporation, lm4934rlx Datasheet - Page 34

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lm4934rlx

Manufacturer Part Number
lm4934rlx
Description
3d Audio Sub-system With Stereo Speaker, Ocl/se Stereo Headphone, Earpiece And Mono Line Level Outputs
Manufacturer
National Semiconductor Corporation
Datasheet

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Application Information
I
The LM4934 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 3.072MHz
(48kHz stereo, 32bit). The basic format is shown below:
NATIONAL SEMICONDUCTOR 3D AUDIO ENHANCEMENT
The LM4934 utilizes a programmable gain version of National Semiconductor’s 3D audio enhancement circuit. This allows 3D
gain only (not frequency response) to be controlled via I2C/SPI in the National 3D Enhancement Level Select registers (3D1 and
3D0). Also, this circuit uses the same 3D path for both the headphone and stereo loudspeaker outputs, so the 3D effect remains
constant when switching from headphone to stereo loudspeaker outputs unless changed in the registers. An added benefit of this
is that the gain of the original signal is unaffected when 3D is turned on/off.
3D gain is established internally with R
but may varied for altered 3D response.
Gain Considerations
When using the mixer and 2,3,4, or 5 channels are summed into the stereo output (headphone or speaker), the gain of each
individual input is automatically reduced by 1/N, where N is the number of channels being summed. This has the effect of
maintaining the total signal output level for different modes (i.e.; when LIN and RIN are summed for a mono output, gain for RIN
and LIN will each be reduced by 6dB). This is not true for mono output modes, like EP and lineout. For these cases, stereo inputs
are treated as one input with a –6dB gain for each input before summing this with a mono input. An example of relative output
levels for each mode is given below:
LM4934 DEMOBOARD OPERATION
BOARD LAYOUT
DIGITAL SUPPLIES
JP14 — Digital Power DVDD
JP14 — I/O Power IOVDD
JP14 — PLL Supply PLLVDD
JP14 — USB Board Supply BBVDD
JP14 — I2C VDD
All supplies may be set independently. All digital ground is common. Jumpers may be used to connect all the digital supplies
together.
S9 – connects VDD_PLL to VDD_D
S10 – connects VDD_D to VDD_IO
S11 – connects VDD_IO to VDD_I2C
2
S
Mode
1
2
3
4
5
6
7
[M+(AL/2)+(AR/2)+(DL/2)+(DR/2)]/2
[(AL/2)+(AR/2)+(DL/2)+(DR/2)]/2
[M+(DL/2)+(DR/2)]/2
[M+(AL/2)+(AR/2)]/2
3D
(AL/2)+(AR+2)
(DL/2)+(DR/2)
Mono Out
(approximately 30kΩ) and externally with C
M
FIGURE 5.
34
(M+AR+DR)/3
Stereo R Out
(AR+DR)/2
(M+AR)/2
(M+DR)/2
3D
DR
AR
M
. Typical values for C
3D
(M+AL+DL)/3
Stereo L Out
(AL+DL)/2
(M+AL)/2
(M+DL)/2
are around 0.22µF,
DL
AL
M
20166907

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