ha9p2425-5 Intersil Corporation, ha9p2425-5 Datasheet - Page 6
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ha9p2425-5
Manufacturer Part Number
ha9p2425-5
Description
3.2 Microsecond Sample And Hold Amplifiers
Manufacturer
Intersil Corporation
Datasheet
1.HA9P2425-5.pdf
(12 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HA9P2425-5
Manufacturer:
HARRIS
Quantity:
20 000
Application Information
Offset Adjustment
The offset voltage of the HA-2420 and HA-2425 may be
adjusted using a 100kΩ trim pot, as shown in Figure 8. The
recommended adjustment procedure is:
Apply 0V to the sample-and-hold input, and a square wave
to the S/H control.
Adjust the trim pot for 0V output in the hold mode.
Gain Adjustment
The linear variation in pedestal voltage with sample-and-hold
input voltage causes a -0.06% gain error (C
some applications (D/A deglitcher, A/D converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold. The
two circuits shown below demonstrate how to adjust gain
error at the sample-and-hold.
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a
5. Measure the output hold voltage (V
+10V output.
-10V output.
the trim pot for an output hold voltage of
(
-----------------------------------------------------------------
V
–
-10
10
FIGURE 5. HOLD STEP vs INPUT VOLTAGE
NOMINAL
HOLD STEP VOLTAGE (mV)
2
-5
)
+
(
-10V
+10
-10
-15
-20
-25
-30
-35
-5
5
0
)
6
+5
DC INPUT VOLTAGE (V)
-10NOMINAL
+10
H
C
C
C
C
= 1000pF). In
H
H
H
H
= 0.1µF
= 10,000pF
= 1000pF
= 100pF
). Adjust
HA-2420, HA-2425
Figure 8 shows a typical unity gain circuit, with Offset
Zeroing. All of the other normal op amp feedback
configurations may be used with the HA-2420, HA-2425. The
input amplifier may be used as a gated amplifier by utilizing
Pin 11 as the output. This amplifier has excellent drive
capabilities along with exceptionally low switch leakage.
The method used to reduce leakage paths on the PC board
and the device package is shown in Figure 9. This guard ring
is recommended to minimize the drift during hold mode.
The hold capacitor should have extremely high insulation
resistance and low dielectric absorption. Polystyrene (below
85
For more applications, consult Intersil Application Note
AN517, or the factory applications group.
INPUT
INPUT
o
CONTROL
C), Teflon, or Parlene types are recommended.
S/H CONTROL INPUT
FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)
FIGURE 7. NON-INVERTING CONFIGURATION
R
R
0.002R
I
I
FIGURE 6. INVERTING CONFIGURATION
IN
100kΩ
OFFSET TRIM (±25mV RANGE)
+IN
-IN
C
I
+
-
R
H
F
-IN
+IN
CONTROL
S/H
R
F
S/H CONTROL
INPUT
V-
CONTROL
+
S/H
-
V+
OUT
NOTE: GAIN ~ 1
NOTE: GAIN
0.002R
OUT
F
OUTPUT
November 19, 2004
∼
OUTPUT
+
–
---------- -
OUT
FN2856.6
R I
R F
------- -
R F
R I