clc407 National Semiconductor Corporation, clc407 Datasheet - Page 4

• Manufacturer Part Number: clc407
• Description: Low-cost, Low-power Programmable Gain Buffer With Disable
• Manufacturer: National Semiconductor Corporation

Closed Loop Gain Selection
The CLC407 is a current feedback op amp with
R
three closed loop gains without using any external gain or
feedback resistors.
-1V/V by connecting pins 2 and 3 as described in the
chart below.
The gain accuracy of the CLC407 is excellent and
stable over temperature change.
setting resistors, R
with a process variation of ± 20% and a temperature
coefficient of ˜ 2000ppm/°C.
values change with processing and temperature, their
ratio (R
used in series with R
will suffer .
Non-Inverting Unity Gain Considerations (A
Achieve a gain of +1V/V by removing all resistive and
capacitive connections between pin 2 and ground plane.
Any capacitive coupling between pin 2 and ground will
cause high frequency peaking in the frequency domain
response and overshoot in the time domain response.
http://www.national.com
CLC407 Typical Performance Characteristics
f
= R
-0.10
-0.20
+1V/V
+2V/V
-1V/V
0.20
0.00
0.10
-0.1
-0.2
Gain
0.2
0.0
0.1
Acl
g
Small Signal Pulse Response
Short Term Settling Time
0
f
/R
= 250
g
) remains constant. If an external resistor is
20
Non-Inverting (pin3)
Time (5ns/div)
on chip (in the package). Select from
40
Time (ns)
input signal
input signal
A
f
A
V
V
+2
and R
-1
ground
g
Implement gains of +2, +1, and
, gain accuracy over temperature
60
V
Input Connections
out
g
= 2Vstep
are diffused silicon resistors
80
Although their absolute
100
Inverting (pin2)
The internal gain
input signal
NC (open)
-1.0
-2.0
2.0
0.0
ground
1.0
CLC407 OPERATION
60
50
40
30
20
10
10k
Large Signal Pulse Response
PSRR and CMRR
v
= +1V/V)
CMRR
PSRR
100k
Frequency (Hz)
Time (5ns/div)
A
A
V
V
+2
-1
1M
4
(A
Minimize this capacitive coupling during layout by removing
ground plane near pins 1, 2, and 3. This minimization
should produce a response similar to the plot labeled
“open” in Graph 1. If desired flatness is greater than plot
“open” in Graph 1, two options remain to further flatten
the frequency response. First, try shorting the inverting
input (pin 2) to the non-inverting input (pin 3).
response is labeled “short” in Graph 1.
inserting a 300
input (pin 2) as shown in Figure 1. This response is
labeled “300 ” in Graph 1. Notice an “open” produces a
response with obvious peaking and maximum bandwidth,
a “short” minimizes peaking and bandwidth, and finally
300 slightly extends bandwidth with minimal peaking.
V
= +2, R
10M
f
= 250 : V
100M
Frequency Response vs.
Unity Gain Configuration
1
-1.0
resistor R between the non-inverting
cc
4.0
3.0
2.0
1.0
50
40
30
20
10
0
0
Frequency (MHz)
-60
= + 5V, R
10
Settling Time vs. Capacitive Load
I
BI
, I
250
CLC407
Graph 1
+
BN
-
10
250
, V
-20
IO
I
BI
L
vs. Temperature
Temperature (
R
V
= 100 unless specified)
s
o
C
V
Short
= 2V step
L
IO
Open
20
C
L
100
1k
(pF)
R
300
s
60
100
I
BN
o
T
C)
s
100
Next, try
1000
140
80
0
-4.0
100
60
40
20
1.0
0
-1.0
-2.0
-3.0
This