SI52142-A01AGM Silicon_Laboratories, SI52142-A01AGM Datasheet - Page 8

• Manufacturer Part Number: SI52142-A01AGM
• Description: Specifications: Type: Clock/Frequency Generator, Fanout Buffer (Distribution), Multiplexer ; PLL: Yes with Bypass ; Main Purpose: PCI Express (PCIe) ; Input: Clock, Crystal ; Output: Clock ; Number of Circuits: 1 ; Ratio - Input Output: 1 3 ; Differe
• Manufacturer: Silicon_Laboratories

Si52142
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2.
2.2. OE Clarification
The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE
pin needs to be logic high and the I
the output clocks: the OE is pulled to a logic low, or the I
to be driven at all time and even though it has an internally 100 k resistor.
2.3. OE Assertion
The OE signals are active high input used for synchronous stopping and starting the output clocks respectively while
the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high causes
stopped respective output clocks to resume normal operation. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output clock
cycles.
2.4. OE Deassertion
When the OE pin is deasserted by making its logic low, the corresponding output clocks are stopped cleanly, and
the final output state is driven low.
2.5. SS[1:0] Clarification
SS[1:0] are active inputs used to select differential output frequency and enable spread of –0.5% on all DIFF
outputs as per Table 5.
8
CLe





CL: Crystal load capacitance
CLe: Actual loading seen by crystal using standard value trim capacitors
Ce: External trim capacitors
Cs: Stray capacitance (terraced)
Ci : Internal capacitance (lead frame, bond wires, etc.)
Total Capacitance (as seen by the crystal)
=
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
Ce = 2 x CL – (Cs + Ci)
1
SS1
0
0
1
1
Table 5. SS0 and SS1 Frequency/Spread Selection
+
1
Ce2 + Cs2 + Ci2
SS0
2
0
1
0
1
C output enable bit needs to be logic high. There are two methods to disable
1
Differential
Frequency
100 MHz
100 MHz
125 MHz
200 MHz
)
Preliminary 0.1
2
C enable bit is set to a logic low. The OE pins is required
Differential
Spread Off
Spread Off
Spread Off
Spread
–0.50%
Configuration
Default