sae81c80a Infineon Technologies Corporation, sae81c80a Datasheet - Page 14

• Manufacturer Part Number: sae81c80a
• Description: Cmos Dual-port Ram
• Manufacturer: Infineon Technologies Corporation

Scheduling Registers
Note: The assignment of a memory area to a scheduling register is defined by the user
With the scheduling registers synchronization can be done with only one access
because the reservation is performed during reading. The other port cannot overwrite it.
This means that a scheduling register is written by reading, unless it was occupied.
The description above shows that these registers are no ordinary RAM locations. They
are formed by a finite state machine (FSM), which can assume the following four states
(see figure 6):
The state of a register can be read out from the particular address, but causes also a
change in the state of the FSM (arrows in figure 6). Reading produces 2-bit information:
Reserving is done by reading a register and enabling by writing to it XXXXXX11
attention to the interrupt outputs of bits 2 and 3!). Thus a correct protocol using the
scheduling registers takes the following form:
1. Read the scheduling register.
2. Check whether the occupied bit is set and the owner bit is not set (i.e. the other port
3. Process the data area.
4. Enable the scheduling register by writing 03
5. End
In cases where accessing of a data area requires prior reading of or writing to this data
area by the second processor, a separate evaluation of the occupied bit and owner bit
can be done in step 2:
2a. Owner bit self? If so, continue to 2c, otherwise to 2b.
2b. Occupied bit self? If so, continue to 2c, otherwise to 3.
2c. Enable the scheduling register by writing 03
Semiconductor Group
– State 1: port 1 was the previous owner and the register is free.
– State 2: port 1 occupies the register.
– State 3: port 2 was the previous owner and the register is free.
– State 4: port 2 occupies the register.
– Bit 0 is the owner bit. It is set when the reading port is or was the owner of a register.
– Bit 1 is the occupied bit. It is set when a register has been reserved by a port.
– Bit 2 through 7 are always 0.
has reserved). If so, go back to 1, otherwise continue.
with 1).
software of both controllers
14
H
H
to the address of the register
to the address of the register (continue
SAE 81C80 A
B
(pay