adcmp581 Analog Devices, Inc., adcmp581 Datasheet
adcmp581
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adcmp581 Summary of contents
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... The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage comparators fabricated on the Analog Devices, Inc. proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP580 features CML output drivers, the ADCMP581 features reduced swing ECL (negative ECL) output drivers, and the ADCMP582 features reduced swing PECL (positive ECL) output drivers ...
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... ADCMP580/ADCMP581/ADCMP582 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Information ......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Considerations.............................................................. 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 8/07—Rev Rev. A Changes to Figure 1.......................................................................... 1 Changes to Table 4............................................................................ 7 Changes to Figure 9.......................................................................... 8 Changes to Figure 21, Figure 22, and Figure 23 ...
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... Latch Minimum Pulse Width ADCMP580 (CML) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP581 (NECL) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP582 (PECL) Latch Enable Input Range ...
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... Rise/Fall Time POWER SUPPLY Positive Supply Voltage Negative Supply Voltage ADCMP580 (CML) Positive Supply Current Negative Supply Current Power Dissipation ADCMP581 (NECL) Positive Supply Current Negative Supply Current Power Dissipation ADCMP582 (PECL) Logic Supply Voltage Input Supply Current Output Supply Current ...
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... TIMING INFORMATION Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the terms shown in Figure 2. LATCH ENABLE LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q OUTPUT Q OUTPUT Table 2. Timing Descriptions Symbol Timing t Input-to-Output High Delay PDH t Input-to-Output Low Delay ...
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... Exposure to absolute −0 +6.0 V maximum rating conditions for extended periods may affect device reliability. −3 +4.0 V THERMAL CONSIDERATIONS − −2 +5.5 V The ADCMP580/ADCMP581/ADCMP582 16-lead LFCSP option has a θ −5 +0.5 V 70°C/W in still air ESD CAUTION −25 mA −40 mA − ...
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... Termination Return Pin for the LE/LE Input Pins. TT For the ADCMP580 (CML output stage), this pin should be connected to the GND ground. For the ADCMP581 (ECL output stage), this pin should be connected to the –2 V termination potential. For the ADCMP582 (PECL output stage), this pin should be connected to the GND/V Digital Ground Pin/Positive Logic Power Supply Terminal ...
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... V vs. TEMPERATURE OH –0.9 OUTPUT (NECL) –1.0 –1.1 –1.2 V vs. TEMPERATURE OL –1.3 OUTPUT (NECL) –1.4 –1.5 –55 –5 45 TEMPERATURE (°C) Figure 7. ADCMP581 Output Voltage vs. Temperature 100 200 300 –IHYST (µA) Figure 8. Hysteresis vs. −IHYST = 25°C, unless otherwise noted ...
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... Figure 14. Dispersion vs. Overdrive ADCMP580/ADCMP581/ADCMP582 –55 500mV M1 M1 500mV 200 250 Rev Page –35 – 105 TEMPERATURE (°C) Figure 15. ADCMP581 t /t vs. Temperature R F 20ps/DIV Figure 16. ADCMP582 Eye Diagram at 2.5 Gbps Q RISE Q RISE Q FALL Q FALL 125 ...
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... V EE Figure 21. Disabling the Latch Feature on the ADCMP580 V P ADCMP581 V N 50Ω 750Ω – Figure 22. Disabling the Latch Feature on the ADCMP581 V P ADCMP582 V N 50Ω 750Ω CCO TT CCO Figure 23. Disabling the Latch Feature on the ADCMP582 CML 50Ω ...
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... LE pin to ground. To prevent excessive power dissipation, the resistor should be 1 kΩ for the ADCMP580. When using the ADCMP581 comparators, the latch can be disabled by connecting the LE pin to V resistor and leaving the LE pin connected to −2 V. The idea is to create an approximate 0 ...
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... ADCMP580/ADCMP581/ADCMP582 OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power, and ground impedances or other layout issues can severely limit performance and can cause oscillation. Discontinuities along input and output transmission lines can also severely limit the specified pulse width dispersion performance ...
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... Devices are not characterized this , a variable amount EE way but simply bypassing a reference input close to the package can reduce jitter 30% in low slew rate applications. Rev Page ADCMP580/ADCMP581/ADCMP582 and has ...
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... ADCMP581BCP–R2 −40°C to +125°C ADCMP581BCP–RL7 −40°C to +125°C 1 ADCMP581BCPZ-WP −40°C to +125°C 1 ADCMP581BCPZ–R2 −40°C to +125°C 1 ADCMP581BCPZ–RL7 −40°C to +125°C ADCMP582BCP-WP −40°C to +125°C ADCMP582BCP-R2 −40°C to +125°C ADCMP582BCP-RL7 − ...
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... NOTES ADCMP580/ADCMP581/ADCMP582 Rev Page ...
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... ADCMP580/ADCMP581/ADCMP582 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04672-0-8/07(A) T Rev Page ...