adcmp581 Analog Devices, Inc., adcmp581 Datasheet - Page 5

• Manufacturer Part Number: adcmp581
• Description: Ultrafast Sige Voltage Comparator
• Manufacturer: Analog Devices, Inc.

TIMING INFORMATION
Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the
terms shown in Figure 2.
Table 2. Timing Descriptions
Symbol
t
t
t
t
t
t
t
t
t
V
V
PDH
PDL
PLOH
PLOL
H
PL
S
R
F
N
OD
Timing
Input-to-Output High Delay
Input-to-Output Low Delay
Latch Enable-to-Output High Delay
Latch Enable-to-Output Low Delay
Minimum Hold Time
Minimum Latch Enable Pulse Width
Minimum Setup Time
Output Rise Time
Output Fall Time
Normal Input Voltage
Voltage Overdrive
INPUT VOLTAGE
LATCH ENABLE
LATCH ENABLE
DIFFERENTIAL
Q OUTPUT
Q OUTPUT
V
N
Description
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
Minimum time that the latch enable signal must be high to acquire an input signal change.
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
Difference between the input voltages V
Difference between the input voltages V
Figure 2. Comparator Timing Diagram
V
t
S
OD
t
t
PDL
PDH
Rev. A | Page 5 of 16
t
H
t
R
t
F
ADCMP580/ADCMP581/ADCMP582
t
PL
t
t
PLOH
PLOL
P
P
and V
and V
N
N
for output true.
for output false.
50%
V
50%
50%
N
± V
OS