adcmp572 Analog Devices, Inc., adcmp572 Datasheet
adcmp572
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adcmp572 Summary of contents
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... High speed latch and programmable hysteresis features are also provided. The ADCMP572 and ADCMP573 are available in a 16-lead LFCSP package and have been characterized over an extended industrial temperature range of −40°C to +125°C. ...
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... ADCMP572/ADCMP573 TABLE OF CONTENTS Electrical Characteristics ................................................................. 3 Absolute Maximum Ratings............................................................ 5 Thermal Considerations.............................................................. 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Application Information.................................................................. 9 Power/Ground Layout and Bypassing ....................................... 9 CML/RSPECL Output Stage ....................................................... 9 REVISION HISTORY 4/05—Revision 0: Initial Version Using/Disabling the Latch Feature..............................................9 Optimizing High Speed Performance ..................................... 10 Comparator Propagation Delay Dispersion ...
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... Latch Setup Time Latch Hold Time Latch Enable Input Impedance Latch to Output Delay Latch Minimum Pulse Width DC OUTPUT CHARACTERISTICS ADCMP572 (CML) Output Impedance Output Voltage High Level Output Voltage Low Level Output Voltage Differential ADCMP573 (RSPECL) Output Voltage High −40°C Output Voltage High +25° ...
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... Minimum Pulse Width Rise Time Fall Time POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential ADCMP572 (CML) Positive Supply Current Device Power Dissipation ADCMP573 (RSPECL) Positive Supply Current Device Power Dissipation 1 Equivalent input bandwidth assumes a simple first-order response and is calculated with the following formula: BW ...
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... V to +3.5 V THERMAL CONSIDERATIONS −0 0.5 V CCI ±(V + 0.5 V) The ADCMP572/ADCMP573 LFCSP 16-lead package has a θ CCI −0 0.5 V (junction-to-ambient thermal resistance) of 70°C/W in still air. CCO −0 +1.5 V ±1 mA ±20 mA − ...
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... V /V Termination Return Pin for the LE/LE Input Pins. CCO TT For the ADCMP572 (CML output stage), this pin is internally connected to and also should be externally connected to the positive V For the ADCMP573 (RSPECL output stage), this pin should normally be connected to the V termination potential Positive Supply Voltage for the CML/RSPECL Output Stage ...
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... Figure 4. Propagation Delay vs. Input Common-Mode 160 158 156 154 152 150 148 146 –60 –40 – TEMPERATURE (°C) Figure 5. Propagation Delay vs. Temperature 200 250 0.8 1.0 1 100 Rev Page ADCMP572/ADCMP573 39.0 38.5 38.0 37.5 37.0 36.5 36.0 –60 –40 – TEMPERATURE (°C) Figure 6. Rise/Fall Time vs. Temperature ...
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... Rev Page –60 –40 – TEMPERATURE (°C) Figure 12. Output Levels vs. Temperature 496.0mV M1 504.0mV 60.00ps/DIV Figure 13. ADCMP572 Eye Diagram at 2.5 Gbps 500.0mV 500.0mV 25.00ps/DIV Figure 14. ADCMP572 Eye Diagram at 6.5 Gbps 80 100 ...
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... CML/RSPECL OUTPUT STAGE Specified propagation delay dispersion performance can be achieved only by using proper transmission line terminations. The outputs of the ADCMP572 are designed to directly drive 400 mV into 50 Ω cable, microstrip, or strip line transmission lines properly terminated to the V supply plane. The CML ...
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... The ADCMP572/ADCMP573 comparators provide internal 50 Ω termination resistors for both the V V inputs, and the ADCMP572 provides 50 Ω back terminated N outputs. The return side for each input termination is pinned out separately with the V and V pins, respectively Ω ...
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... The external feedback network can also introduce significant parasitics, which reduce high speed performance and can even induce oscillation in some cases. The ADCMP572/ADCMP573 comparators offer a program- mable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. By connecting an external pull-down resistor from the HYS pin to GND, a variable amount of hysteresis can be applied ...
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... Figure 25. Interfacing 3.3 V CML Ω Ground Terminated Instrument V CCI V = 3.3V V CCO CCO 50Ω ADCMP572 CCO 750Ω Figure 26. Disabling the ADCMP572 Latch Feature CCI CCO V P ADCMP573 V N 50Ω 3.2V TT 500Ω V CCO Figure 27. Disabling the ADCMP573 Latch Feature ...
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... TIMING INFORMATION Figure 29 illustrates the ADCMP572/ADCMP573 compare and latch timing relationships. Table 4 provides definitions of the terms shown in the figure. LATCH ENABLE LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q OUTPUT Q OUTPUT Table 4. Timing Descriptions Symbol Timing t Input to output high delay PDH t Input to output low delay ...
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... SEATING PLANE ORDERING GUIDE Model Temperature Range ADCMP572BCP-WP −40°C to 85°C ADCMP572BCP-R2 −40°C to 85°C ADCMP572BCP-RL7 −40°C to 85°C EVAL-ADCMP572BCP ADCMP573BCP-WP −40°C to 85°C ADCMP573BCP-R2 −40°C to 85°C ADCMP573BCP-RL7 −40°C to 85°C EVAL-ADCMP573BCP 3.00 0.60 MAX BSC SQ ...
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... NOTES Rev Page ADCMP572/ADCMP573 ...
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... ADCMP572/ADCMP573 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04409–0–4/05(0) Rev Page ...