lm21215a-1 National Semiconductor Corporation, lm21215a-1 Datasheet - Page 10

• Manufacturer Part Number: lm21215a-1
• Description: 15a High Efficiency Synchronous Buck Regulator With Frequency Synchronization
• Manufacturer: National Semiconductor Corporation

www.national.com
Operation Description
GENERAL
The LM21215A-1 switching regulator features all of the func-
tions necessary to implement an efficient low voltage buck
regulator using a minimum number of external components.
This easy to use regulator features two integrated switches
and is capable of supplying up to 15A of continuous output
current. The regulator utilizes voltage mode control with trail-
ing edge modulation to optimize stability and transient re-
sponse over the entire output voltage range. The device can
operate at high switching frequency allowing use of a small
inductor while still achieving high efficiency. The precision in-
ternal voltage reference allows the output to be set as low as
0.6V. Fault protection features include: current limiting, ther-
mal shutdown, over voltage protection, and shutdown capa-
bility. The device is available in the eTSSOP-20 package
featuring an exposed pad to aid thermal dissipation. The
LM21215A-1 can be used in numerous applications to effi-
ciently step-down from a 5V or 3.3V bus.
FREQUENCY SYNCHRONIZATION
The sync (SYNC) pin allows the LM21215A-1 to be switched
at an external clock frequency. When a clock signal is present
on the SYNC pin within the allowable frequency range, 300
kHz to 1.5 MHz, the device will synchronize the turn-on of the
high side FET (switch rising) to the negative edge of the clock
signal, as seen in
LM21215A-1 will default to a switching frequency of 500 kHz.
The clock signal can be present on the SYNC pin before the
device is powered on with no loading on the clock signal. Al-
ternatively, if no clock is present while the device is powered
up, it will begin switching at the default frequency of 500 kHz.
Once the clock signal is present, the device will begin syn-
chronizing to the clock frequency. The length of time neces-
sary for the synchronization depends on the clock frequency.
FIGURE 1. Frequency synchronization
Figure 1
. If no clock signal is present, the
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PRECISION ENABLE
The enable (EN) pin allows the output of the device to be en-
abled or disabled with an external control signal. This pin is a
precision analog input that enables the device when the volt-
age exceeds 1.35V (typical). The EN pin has 110 mV of
hysteresis and will disable the output when the enable voltage
falls below 1.24V (typical). If the EN pin is not used, it can be
left open, and will be pulled high by an internal 2 µA current
source. Since the enable pin has a precise turn-on threshold
it can be used along with an external resistor divider network
from VIN to configure the device to turn-on at a precise input
voltage.
UVLO
The LM21215A-1 has a built-in under-voltage lockout protec-
tion circuit that keeps the device from switching until the input
voltage reaches 2.7V (typical). The UVLO threshold has 200
mV of hysteresis that keeps the device from responding to
power-on glitches during start up. If desired the turn-on point
of the supply can be changed by using the precision enable
pin and a resistor divider network connected to VIN as shown
in
CURRENT LIMIT
The LM21215A-1 has current limit protection to avoid dan-
gerous current levels on the power FETs and inductor. A
current limit condition is met when the current through the high
side FET exceeds the rising current limit level (I
trol circuitry will respond to this event by turning off the high
side FET and turning on the low side FET. This forces a neg-
ative voltage on the inductor, thereby causing the inductor
current to decrease. The high side FET will not conduct again
until the lower current limit level (I
side FET. At this point, the device will resume normal switch-
ing.
A current limit condition will cause the internal soft-start volt-
age to ramp downward. After the internal soft-start ramps
below the Feedback (FB) pin voltage, (nominally 0.6 V), FB
will begin to ramp downward, as well. This voltage foldback
will limit the power consumption in the device, thereby pro-
tecting the device from continuously supplying power to the
load under a condition that does not fall within the device
SOA. After the current limit condition is cleared, the internal
soft-start voltage will ramp up again.
limit behavior with V
Figure 6
in the design guide.
SS
, V
FB
, V
OUT
and V
CLF
Figure 2
) is sensed on the low
SW
.
shows current
CLR
). The con-