74aup2g00 NXP Semiconductors, 74aup2g00 Datasheet
74aup2g00
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74aup2g00 Summary of contents
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... Low-power dual 2-input NAND gate Rev. 02 — 15 May 2007 1. General description The 74AUP2G00 provides the dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V This device ensures a very low static and dynamic power consumption across the entire V range from 0 ...
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... Fig 1. Logic symbol 6. Pinning information 6.1 Pinning Fig 4. Pin configuration SOT765-1 (VSSOP8) 74AUP2G00_2 Product data sheet Description VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 XQFN8 plastic extremely thin quad fl ...
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... Fig 6. Pin configuration SOT902-1 (XQFN8) SOT902 Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate 74AUP2G00 terminal 1 index area Transparent top view Description data input data input data output ground (0 V) ...
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... +125 C amb derates linearly with 8.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode 0 3 Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate Min Max Unit 0.5 +4 [1] 0.5 +4 [1] ...
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... GND GND GND Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate Min Typ Max 0.7 ...
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... 3 0 GND Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate Min Typ Max ...
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... 3 0 GND GND. CC Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate Min Typ Max ...
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... 1 1. 2 3.6 V 1.6 CC [2] Figure 1 1 1. 2 3.6 V 2.3 CC Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate +125 C [1] Typ Max Min Max ( 17 5.3 11.0 2.1 12.2 3.8 6.8 1.8 7.8 3.1 5.3 1.4 6.2 2.5 4.0 1.1 4.7 2.2 3.6 1 ...
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... W where nA, nB input M t PHL nY output V M Table 9. Input 0 Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate +125 C [1] Typ Max Min Max ( ...
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... PULSE DUT GENERATOR for measuring propagation delays, setup and hold times and pulse width R L Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate V EXT 001aac521 of the pulse generator EXT ...
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... Product data sheet 2.5 scale (1) ( 0.27 0.23 2.1 2.4 0.5 0.17 0.08 1.9 2.2 REFERENCES JEDEC JEITA MO-187 Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate detail 3.2 0.40 0.21 0.4 0.2 0.13 0.15 0.19 3.0 EUROPEAN PROJECTION SOT765-1 v ...
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... scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA - - - MO-252 Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate 4 ( EUROPEAN PROJECTION © NXP B.V. 2007. All rights reserved. SOT833-1 ISSUE DATE 04-07-22 04-11- ...
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... 1.65 0.35 0.15 0.55 0.5 0.1 1.55 0.25 0.05 REFERENCES JEDEC JEITA MO-255 - - - Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate detail 0.05 0.05 0.05 EUROPEAN PROJECTION SOT902 ISSUE DATE 05-11-16 05-11-25 © NXP B.V. 2007. All rights reserved. ...
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... Changed: ESD HBM exceeds 5000 V. 74AUP2G00_1 20060825 74AUP2G00_2 Product data sheet Data sheet status Product data sheet “Features”: Product data sheet Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate Change notice Supersedes - 74AUP2G00_1 - - © NXP B.V. 2007. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 15 May 2007 74AUP2G00 Low-power dual 2-input NAND gate © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 15 May 2007 Document identifier: 74AUP2G00_2 ...