74avch1t45 NXP Semiconductors, 74avch1t45 Datasheet

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... In suspend mode when either V GND level, both A and B are in the high-impedance OFF-state. The 74AVCH1T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors ...

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... C to +125 C 4. Marking Table 2. Marking Type number 74AVCH1T45GW 74AVCH1T45GM 5. Functional diagram 5 DIR CC(A) Fig 1. Logic symbol 74AVCH1T45_1 Product data sheet Description SC-88 plastic surface-mounted package; 6 leads XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 Marking code CC(B) 001aag885 Fig 2. Logic diagram Rev. 01 — ...

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... Fig 4. Pin configuration SOT886 Description supply voltage port A and DIR ground (0 V) data input or output data input or output direction control supply voltage port B Input/output input Z . CC(A) Rev. 01 — 25 October 2007 74AVCH1T45 74AVCH1T45 CC(A) CC(B) GND 2 5 DIR 001aag888 Transparent top view ...

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... Suspend or 3-state mode CC(A) CC( +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Suspend or 3-state mode 3.6 V CCI Rev. 01 — 25 October 2007 74AVCH1T45 Min Max Unit 0.5 +4.6 V 0.5 +4 [1] 0 0.5 ...

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... 3 0 3.6 V CC 3.6 V CC( 3 3.3 V CC( 3.3 V CC( 3.6 V Rev. 01 — 25 October 2007 74AVCH1T45 Min Typ Max - 0. 0. 0.025 [2] - 0.5 2.5 - ...

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... CC(A) CC( mA 3.0 V CC(A) CC 3.6 V CC( 1.4 V CC(A) CC( 1.65 V CC(A) CC( 2.3 V CC(A) CC( 3.0 V CC(A) CC( 1.4 V CC(A) CC( 1.65 V CC(A) CC( 2.3 V CC(A) CC( 3.0 V CC(A) CC(B) Rev. 01 — 25 October 2007 74AVCH1T45 Min Typ Max [ 0.30 V CCI - - 0.35 V CCI - - 0 0 0.30 V CC( 0.35 V CC( 0 0.9 [ CCO ...

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... A I CCI 0 3.6 V CC( CC( 3.6 V CC( CC(A) CC( CCI = 3.6 V CC( 3.6 V Rev. 01 — 25 October 2007 74AVCH1T45 Min Typ Max [1] 125 - - 200 - - 300 - - 500 - - [1] 125 - - 200 - - 300 - - 500 - - [ ...

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... CC(A) CC( mA 3.0 V CC(A) CC 3.6 V CC( 1.4 V CC(A) CC( 1.65 V CC(A) CC( 2.3 V CC(A) CC( 3.0 V CC(A) CC( 1.4 V CC(A) CC( 1.65 V CC(A) CC( 2.3 V CC(A) CC( 3.0 V CC(A) CC(B) Rev. 01 — 25 October 2007 74AVCH1T45 Min Typ Max [ 0.30 V CCI - - 0.35 V CCI - - 0 0 0.30 V CC( 0.35 V CC( 0 0.9 [ CCO ...

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... CCI 0 3.6 V CC( CC( 3.6 V CC( CCI 0 3.6 V CC( CC( 3.6 V CC( CC(A) CC( CCI = 3.6 V CC(B) Rev. 01 — 25 October 2007 74AVCH1T45 Min Typ Max [1] 125 - - 200 - - 300 - - 500 - - [1] 125 - - 200 - - 300 - - 500 - - [ 7 ...

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... PLZ PHZ en Section 13.4 “Enable times” and T CC(A) CC(B) 0 where ns pF Rev. 01 — 25 October 2007 74AVCH1T45 Dual supply translating transceiver; 3-state [ for wave forms see Figure 5 and V CC(B) 1.5 V 1.8 V 2.5 V 8.0 8.0 8.7 12.4 12.2 12.0 12.2 12.2 12.2 7.6 8.2 8.7 20.0 20.4 20.7 20.2 20.2 20 ...

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... Min 1.0 9.0 0.7 6.8 1.0 9.0 0.8 8.0 2.2 8.8 2.2 8.8 2.2 8.4 1.8 6.7 - 17.4 - 14.7 - 17.8 - 15.6 1.0 8.0 0.7 5.4 1.0 6.8 0.8 5.4 1.6 6.3 1.6 6.3 2.0 7.6 1.8 5.9 - 14.4 - 11.3 - 14.3 - 11.7 1.0 7.7 0.6 5.1 1.0 6.1 0.7 4.6 1.6 5.5 1.6 5.5 1.8 7.8 1.8 5.7 - 13.9 - 10.3 - 13.2 - 10.6 1.0 7.2 0.5 4.7 1.0 5.7 0.6 3.8 1.5 4.2 1.5 4.2 1.7 7.3 2.0 5.2 - 13.0 - 9.0 - 11.4 - 8.9 1.0 7.1 0.5 4.5 1.0 6.1 0.6 3.6 1.5 4.7 1.5 4.7 1.7 7.2 0.7 5.5 - 13.3 - 9.1 - 11.8 - 9.2 is the same as t and the same as t PLZ PHZ en Section 13.4 “Enable times” Rev. 01 — 25 October 2007 74AVCH1T45 Dual supply translating transceiver; 3-state [1] 7; for wave forms see Figure 5 and V CC(B) 0.15 V 2.5 V 0.2 V 3.3 V Max Min Max Min 0.6 6.1 0.5 5.7 0.5 0.7 7.7 0.6 7.2 0.5 2.2 8.8 2.2 8.8 2.2 2.0 6.9 1.7 6.2 2.4 - 14 14.9 - 14.5 - 0.6 4.6 0.5 3.7 0.5 0.7 5.1 0.6 4.7 0.5 1.6 6.3 1.6 6.3 1.6 1.6 6.0 1.2 4.8 1.7 - 11 10.9 - 10.0 - 0.5 4.3 0.5 3.4 0.5 0.5 4.4 0.5 3.9 0.5 1.6 5.5 1.6 5.5 1.6 1.4 5.8 1.0 4.5 1.5 - 10 9.8 - 8.9 - 0.5 3.9 0.5 3.0 0.5 0.5 3.4 0.5 3.0 0.5 1.5 4.2 1.5 4.2 1.5 1.5 5.1 0.6 4.2 1.1 - 8 ...

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... Min 1.0 9.9 0.7 7.5 1.0 9.9 0.8 8.8 2.2 9.7 2.2 9.7 2.2 9.2 1.8 7.4 - 19.1 - 16.2 - 19.6 - 17.2 1.0 8.8 0.7 6.0 1.0 7.5 0.8 6.0 1.6 7.0 1.6 7.0 2.0 8.3 1.8 6.5 - 15.8 - 12.5 - 15.8 - 13.0 1.0 8.5 0.6 5.7 1.0 6.8 0.7 5.1 1.6 6.1 1.6 6.1 1.8 8.6 1.8 6.3 - 15.4 - 11.4 - 14.6 - 11.8 1.0 8.0 0.5 5.2 1.0 6.3 0.6 4.2 1.5 4.7 1.5 4.7 1.7 8.0 2.0 5.8 - 14.3 - 10.0 - 12.7 - 9.9 1.0 7.9 0.5 5.0 1.0 6.8 0.6 4.0 1.5 5.2 1.5 5.2 1.7 7.9 0.7 6.0 - 14.7 - 10.1 - 13.1 - 10.2 is the same as t and the same as t PLZ PHZ en Section 13.4 “Enable times” Rev. 01 — 25 October 2007 74AVCH1T45 Dual supply translating transceiver; 3-state [1] 7; for wave forms see Figure 5 and V CC(B) 0.15 V 2.5 V 0.2 V 3.3 V Max Min Max Min 0.6 6.8 0.5 6.3 0.5 0.7 8.5 0.6 8.0 0.5 2.2 9.7 2.2 9.7 2.2 2.0 7.6 1.7 6.9 2.4 - 16 16.5 - 16.0 - 0.6 5.1 0.5 4.1 0.5 0.7 5.7 0.6 5.2 0.5 1.6 7.0 1.6 7.0 1.6 1.6 6.6 1.2 5.3 1.7 - 12 12.7 - 11.1 - 0.5 4.8 0.5 3.8 0.5 0.5 4.9 0.5 4.3 0.5 1.6 6.1 1.6 6.1 1.6 1.4 6.4 1.0 5.0 1.5 - 11 10.9 - 9.9 - 0.5 4.3 0.5 3.3 0.5 0.5 3.8 0.5 3.3 0.5 1.5 4.7 1.5 4.7 1.5 1.5 5.7 0.6 4.7 1.1 - 9 ...

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... V CCO PHZ GND outputs outputs enabled disabled Table 13. [2] Output V M 0.5 V CCO 0.5 V CCO 0.5 V CCO Rev. 01 — 25 October 2007 74AVCH1T45 t PLH 001aae967 t PZL PZH V M outputs enabled 001aae968 ...

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... M pulse DUT R T Load Rev. 01 — 25 October 2007 74AVCH1T45 EXT 001aae331 V EXT PLH PHL PZH PHZ PZL open ...

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... CC(A) 2 GND DIR CC(B) 74AVCH1T45_1 Product data sheet Dual supply translating transceiver; 3-state Figure example of the 74AVCH1T45 being used in an 74AVCH1T45 VCC1 V CC(A) 1 GND 2 VCC1 A 3 system-1 Description unidirectional logic level-shifting application Function Description V supply voltage of system-1 (0 3.6 V) ...

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... NXP Semiconductors 13.2 Bidirectional logic level-shifting application Figure 9 shows the 74AVCH1T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. ...

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... In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVCH1T45 initially is transmitting from then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specifi ...

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... scale 2.2 1.35 2.2 0.45 1.3 0.65 1.8 1.15 2.0 0.15 REFERENCES JEDEC JEITA SC-88 Rev. 01 — 25 October 2007 74AVCH1T45 detail 0.25 0.2 0.2 0.1 0.15 EUROPEAN ISSUE DATE PROJECTION 04-11-08 06-03-16 © NXP B.V. 2007. All rights reserved. SOT363 ...

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... Product data sheet scale 0.35 0.40 0.6 0.5 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 01 — 25 October 2007 74AVCH1T45 Dual supply translating transceiver; 3-state 4 ( EUROPEAN ISSUE DATE PROJECTION 04-07-15 04-07-22 © NXP B.V. 2007. All rights reserved. SOT886 ...

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... Machine Model 16. Revision history Table 19. Revision history Document ID Release date 74AVCH1T45_1 20071025 74AVCH1T45_1 Product data sheet Dual supply translating transceiver; 3-state Data sheet status Change notice Product data sheet - Rev. 01 — 25 October 2007 74AVCH1T45 Supersedes - © NXP B.V. 2007. All rights reserved ...

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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 25 October 2007 74AVCH1T45 © NXP B.V. 2007. All rights reserved ...

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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: 74AVCH1T45_1 All rights reserved. Date of release: 25 October 2007 ...