74AVCH2T45DC,125 NXP Semiconductors, 74AVCH2T45DC,125 Datasheet
74AVCH2T45DC,125
Specifications of 74AVCH2T45DC,125
74AVCH2T45DC-G
935283721125
Related parts for 74AVCH2T45DC,125
74AVCH2T45DC,125 Summary of contents
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Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 4 — 24 November 2010 1. General description The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a ...
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... NXP Semiconductors 280 Mbps (translate to 1.5 V) 240 Mbps (translate to 1.2 V) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < ...
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... NXP Semiconductors 5. Functional diagram 5 DIR CC(A) Fig 1. Logic symbol 6. Pinning information 6.1 Pinning Fig 3. Pin configuration SOT765-1 74AVCH2T45 V 1 CC( GND 4 Transparent top view Fig 4. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 74AVCH2T45 Product data sheet Dual-bit, dual-supply voltage level translator/transceiver; 3-state ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin V 1 CC( GND 4 DIR CC(B) 7. Functional description [1] Table 4. Function table Supply voltage Input DIR CC(A) CC( [4] GND X [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. [2] The input circuit of the data I/O is always active. ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage A CC(A) V supply voltage B CC(B) I input clamping current IK V input voltage I I output clamping current OK V output voltage ...
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... NXP Semiconductors 10. Static characteristics Table 7. Typical static characteristics recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I bus hold LOW current BHL I bus hold HIGH current BHH ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level data input IH input voltage V CCI V CCI V CCI V CCI DIR input V CC(A) V CC(A) V CC(A) V CC(A) V LOW-level data input IL input voltage V CCI V CCI V CCI V CCI ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage = 100 CC CC CC(A) I input leakage DIR input current V CC(A) I bus hold LOW port BHL current CC( 0. CC( 0.70 V ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I power-off A port; V OFF leakage V CC(A) current B port CC(B) I supply current A port CC(A) V CC(B) V CC(A) V CC(A) B port CC(A) V CC(B) V CC(A) V CC(A) A plus B port ( CC(A) V CC(B) ...
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... NXP Semiconductors 11. Dynamic characteristics Table 9. Typical dynamic characteristics at V Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay disable time DIR to A dis DIR enable time DIR DIR the same as t and PLH PHL ...
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... NXP Semiconductors Dynamic characteristics for temperature range 40 C to +85 C Table 12. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 1.3 V CC(A) t propagation delay disable time DIR to A dis DIR enable time DIR DIR 1 1.6 V ...
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... NXP Semiconductors Dynamic characteristics for temperature range 40 C to +125 C Table 13. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 1.3 V CC(A) t propagation delay disable time DIR to A dis DIR enable time DIR DIR 1 1.6 V ...
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... NXP Semiconductors 12. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 6. The data input (nA, nB) to output (nB, nA) propagation delay times DIR input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...
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... NXP Semiconductors Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance External voltage for measuring switching times. EXT Fig 8. Test circuit for measuring switching times Table 15. Test data Supply voltage Input [ CC(A) CC( 1.6 V ...
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... NXP Semiconductors 13. Application information 13.1 Unidirectional logic level-shifting application The circuit given in unidirectional logic level-shifting application. Fig 9. Table 16. Pin 74AVCH2T45 Product data sheet Dual-bit, dual-supply voltage level translator/transceiver; 3-state Figure example of the 74AVCH2T45 being used CC1 V V CC(A) CC1 GND 4 V CC1 ...
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... NXP Semiconductors 13.2 Bidirectional logic level-shifting application Figure 10 application. Since the device does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. Fig 10. Bidirectional logic level-shifting application Table 17 and then from system-2 to system-1. ...
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... NXP Semiconductors 13.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 18. V CC( 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 13.4 Enable times The enable times for the 74AVCH2T45 are calculated from the following formulas: • ...
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... NXP Semiconductors 14. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 14. Package outline SOT996-2 (XSON8U) ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors 15. Abbreviations Table 19. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 16. Revision history Table 20. Revision history Document ID Release date 74AVCH2T45 v.4 20101124 • Modifications: Added type number 74AVCH2T45GF (SOT1089 / XSON8 package). ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AVCH2T45 Product data sheet Dual-bit, dual-supply voltage level translator/transceiver ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Application information ...