74ALVC16374MTD Fairchild Semiconductor, 74ALVC16374MTD Datasheet

74ALVC16374MTD

Manufacturer Part Number

74ALVC16374MTD

Description

IC FLIP FLOP 16BIT D LV 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74ALVCr

Type

D-Type Busr

Datasheet

1.74ALVC16374MTD.pdf (8 pages)

Specifications of 74ALVC16374MTD

Function

Standard

Output Type

Tri-State Non Inverted

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

200MHz

Delay Time - Propagation

1.3ns

Trigger Type

Positive Edge

Current - Output High, Low

24mA, 24mA

Voltage - Supply

1.65 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74ALVC16374GX

(Note 2)

74ALVC16374MTD

(Note 3)

74ALVC16374

Low Voltage 16-Bit D-Type Flip-Flop

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16374 contains sixteen non-inverting D-type flip-

flops with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. A buffered clock

(CP) and output enable (OE) are common to each byte and

can be shorted together for full 16-bit operation.

The 74ALVC16374 is designed for low voltage (1.65V to

3.6V) V

The 74ALVC16374 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Order Number

applications with I/O compatibility up to 3.6V.

Package Number

BGA54A

MTD48

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500692

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

1.65V - 3.6V V

3.6V tolerant inputs and outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal (Note 1)

Uses patented noise/EMI reduction circuitry

Latchup conforms to JEDEC JED78

ESD performance:

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

3.5 ns max for 3.0V to 3.6V V

4.4 ns max for 2.3V to 2.7V V

7.8 ns max for 1.65V to 1.95V V

Human body model

Machine model

Package Descriptions

supply operation

200V

2000V

through a pull-up resistor; the minimum

October 2001

Revised May 2005

www.fairchildsemi.com

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74ALVC16374MTD Summary of contents

Page 1

... BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 2) [TAPE and REEL] 74ALVC16374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...

Page 2

Logic Symbol Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Clock Pulse Input n I –I Inputs –O ...

Page 3

Functional Description The 74ALVC16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte func- tioning identically, but independent of the other. The control pins can be shorted together ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 5) 0. Input Diode Current ( Output Diode Current ...

Page 5

AC Electrical Characteristics Symbol Parameter V CC Min f Maximum Clock Frequency 250 MAX Propagation Delay PHL PLH 1.3 Bus to Bus Output Enable Time 1.3 PZL PZH Output Disable Time ...

Page 6

AC Loading and Waveforms FIGURE 1. AC Test Circuit Symbol 3. FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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