at49bv6416c ATMEL Corporation, at49bv6416c Datasheet - Page 3

• Manufacturer Part Number: at49bv6416c
• Description: 64-megabit 4m X 16 Page Mode 2.7-volt Flash Memory
• Manufacturer: ATMEL Corporation

3. Device Operation
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3465D–FLASH–04/06
Command Sequences
Asynchronous Read
Page Read
Reset
Erase
Chip Erase
Plane Erase
When the device is first powered on, it will be in the read mode. Command sequences are used
to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. The address is latched on
the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE
pulse, whichever occurs first. The addresses used in the command sequences are not affected
by entering the command sequences.
The AT49BV6416C(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the out-
puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
The page read operation of the device is controlled by CE and OE inputs. The page size is four
words. The first word access of the page read is the same as the asynchronous read. The first
word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1
will result in subsequent reads within the page being output at a speed of 20 ns. See the
Read Cycle Waveform” on page
A Reset input pin is provided to ease some system applications. When Reset is at a logic high
level, the device is in its standard operating mode. A low level on the Reset pin halts the present
device operation and puts the outputs of the device in a high-impedance state. When a high
level is reasserted on the Reset pin, the device returns to read mode.
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a
logical “1”. The entire memory can be erased by using the Chip Erase command or individual
planes can be erased by using the Plane Erase command or individual sectors can be erased by
using the Sector Erase command.
Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the
last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset
during chip erase will stop the erase, but the data will be of an unknown state.
As an alternative to a full Chip Erase, the device is organized into four planes that can be individ-
ually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address
is valid at the second rising edge of WE will be erased. The Plane Erase command does not
alter the data in the protected sectors.
24.
AT49BV6416C(T)
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