at49bv642dt ATMEL Corporation, at49bv642dt Datasheet - Page 11

• Manufacturer Part Number: at49bv642dt
• Description: 64-megabit 4m X 16 3-volt Only Flash Memory
• Manufacturer: ATMEL Corporation

5. Command Definition Table
Notes:
3631A–FLASH–04/06
Command Sequence
Read
Chip Erase
Sector Erase
Word Program
Dual-Word Program
Enter Single-pulse Program
Mode
Single-pulse Word Program
Mode
Sector Lockdown
Erase/Program Suspend
Erase/Program Resume
Product ID Entry
Product ID Exit
Product ID Exit
Program Protection
Register – Block B
Lock Protection
Register – Block B
Status of Block B
Protection
Set Configuration Register
CFI Query
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages
4. The fast programming option enables the user to program two words in parallel only when V
5. Once a sector is in the lockdown mode, the data in the protected sector cannot be changed, unless the chip is reset or power
6. During the fourth bus cycle, the manufacturer code is read from address 00000H, the device code is read from address
7. Either one of the Product ID Exit commands can be used.
8. Bytes of data other than F0 may be used to exit the product ID mode. However, it is recommended that F0 be used.
9. Any address within the user programmable register region. Please see
10. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
11. The default state (after power-up) of the configuration register is “00”.
each bus cycle is as follows: A11 - A0 (Hex), A11 - A21 (Don’t Care).
for details).
and Addr1, of the two words, D
purpose only.
cycled.
00001H, and the data in the protection register is read from addresses 000081H - 000088H.
(7)
(7)
(6)
(5)
(4)
Cycles
Bus
1
6
6
4
5
6
1
6
1
1
3
3
1
4
4
4
4
1
Addr
Addr
Addr
X55
555
555
555
555
555
555
555
555
555
555
555
555
xxx
xxx
xxx
1st Bus
Cycle
D
F0
Data
IN0
AA
AA
AA
AA
AA
D
AA
AA
AA
AA
AA
AA
AA
B0
30
98
OUT
IN
(8)
and D
AAA
Addr
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
IN1
2nd Bus
(2)
Cycle
, must only differ in address A0. This command should be used for manufacturing
Data
55
55
55
55
55
55
55
55
55
55
55
55
Addr
555
555
555
555
555
555
555
555
555
555
555
555
3rd Bus
Cycle
F0
Data
A0
E0
C0
C0
D0
80
80
80
80
90
90
(8)
“Protection Register Addressing Table” on page
Addr
Addr0
Addr
Addr
555
555
555
555
xxx
80
80
(9)
4th Bus
Cycle
00/01
D
OUT
Data
D
D
AA
AA
D
AA
AA
X0
IN0
IN
IN
AT49BV642D(T)
(10)
(11)
PP
= 10V. The addresses, Addr0
Addr1
Addr
AAA
AAA
AAA
AAA
5th Bus
Cycle
Data
D
55
55
55
55
IN1
SA
Addr
SA
555
555
(3)(5)
13
6th Bus
(3)
Cycle
-
16
Data
A0
10
30
60
12.
11