is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet

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is42s16128

Manufacturer Part Number
is42s16128
Description
128k Words Bits Banks Sdram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
is42s16128-10T
Manufacturer:
ISSI
Quantity:
90
Part Number:
is42s16128-10T
Manufacturer:
ISD
Quantity:
128
FEATURES
• Clock frequency: 125 MHz, 100 MHz, 83 MHz
• Two banks can be operated simultaneously and
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Auto refresh, self refresh
• 1K refresh cycles every 16 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Byte controlled by LDQM and UDQM
• Package 400-mil 50-pin TSOP II
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
128K Words x 16 Bits x 2 Banks (4-MBIT)
SYNCHRONOUS DYNAMIC RAM
IS42S16128
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
independently
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
GNDQ
GNDQ
VCCQ
VCCQ
LDQM
VCC
VCC
CAS
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE
CS
A9
A8
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
I/O15
I/O14
GNDQ
I/O13
I/O12
VCCQ
I/O11
I/O10
GNDQ
I/O9
I/O8
VCCQ
NC
UDQM
CLK
CKE
NC
NC
NC
A7
A6
A5
A4
GND
ORDERING INFORMATION
Commercial Range: 0⋅ ⋅ ⋅ ⋅ ⋅ C to 70⋅ ⋅ ⋅ ⋅ ⋅ C
Frequency
125 MHz
100 MHz
83 MHz
DESCRIPTION
ISSI's 4Mb Synchronous DRAM IS42S16128 is organized as
a 131072-word x 16-bit x 2-bank for improved performance.
The synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals refer
to the rising edge of the clock input.
PIN DESCRIPTIONS
A0-A9
A0-A8
A9
A0-A7
I/O0 to I/O15
CLK
CKE
CS
RAS
CAS
WE
LDQM
UDQM
Vcc
GND
VccQ
GNDQ
NC
Speed (ns)
10
12
8
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
IS42S16128-8T
IS42S16128-10T
IS42S16128-12T
Order Part No.
ISSI
FEBRUARY 2000
400-mil TSOP II
400-mil TSOP II
400-mil TSOP II
Package
®
1

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