is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet - Page 29

• Manufacturer Part Number: is42s16128
• Description: 128k Words Bits Banks Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
point where burst input is invalid, i.e., the point where input
data is no longer written to device internal memory is zero
clock cycles regardless of the CAS.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
IS42S16128
CAS latency = 2, 3, burst length = 4
CAS latency = 2, 3, burst length = 4
WDL
COMMAND
) from the precharge command to the
COMMAND
CLK
I/O
DQM
CLK
I/O
WRITE (CA=A, BANK 0)
WRITE A0
D
WRITE (CA=A, BANK 0)
IN
A0
WRITE A0
D
IN
D
IN
A0
A1
D
IN
D
IN
A1
A2
D
IN
D
A2
IN
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual bank
operation.
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (t
precharge command must be executed on one clock
cycle that follows the input of the last burst data item.
t
A3
DPL
PRECHARGE (BANK 0)
D
PRE 0
PRE 0
IN
A3
MASKED BY DQM
CAS Latency
PRECHARGE (BANK 0)
t
WDL
t
t
WDL
DPL
=0
DPL
) has elapsed. Therefore, the
3
0
1
ISSI
2
0
1
29
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