is42s16128 Integrated Silicon Solution, Inc., is42s16128 Datasheet - Page 22

• Manufacturer Part Number: is42s16128
• Description: 128k Words Bits Banks Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

Burst Read
The read cycle is started by executing the read command.
The address provided during read command execution is
used as the starting address. First, the data correspond-
ing to this address is output in synchronization with the
clock signal after the CAS latency period. Next, data
corresponding to an address generated automatically by
the device is output in synchronization with the clock
signal.
The output buffers go to the LOW impedance state CAS
latency minus one cycle after the read command, and go
to the HIGH impedance state automatically after the last
data is output. However, the case where the burst length
Burst Write
The write cycle is started by executing the command. The
address provided during write command execution is
used as the starting address, and at the same time, data
for this address is input in synchronization with the clock
signal.
Next, data is input in other in synchronization with the
clock signal. During this operation, data is written to
address generated automatically by the device. This
cycle terminates automatically after a number of clock
cycles determined by the stipulated burst length. How-
ever, the case where the burst length is a full page is an
exception. In this case the write cycle must be terminated
by executing a burst stop command.
22
IS42S16128
CAS latency = 3, burst length = 4
CAS latency = 2,3, burst length = 4
COMMAND
COMMAND
CLK
CLK
I/O
I/O
D
READ
WRITE
IN
0
CAS LATENCY
BURST LENGTH
D
IN
t
CAC
1
D
IN
2
D
OUT
D
IN
0
3
The latency for I/O pin data input is zero, regardless of the
CAS latency setting. However, a wait period (write recov-
ery: t
to complete the write operation.
Note that the upper byte and lower byte input data can be
masked independently under control of the signals ap-
plied to the U/LDQM pins. The delay period (t
at zero, regardless of the CAS latency setting, when this
function is used.
The selected bank must be set to the active state before
executing this command.
is a full page is an exception. In this case the output
buffers must be set to the high impedance state by
executing a burst stop command.
Note that upper byte and lower byte output data can be
masked independently under control of the signals ap-
plied to the U/LDQM pins. The delay period (t
at two, regardless of the CAS latency setting, when this
function is used.
The selected bank must be set to the active state before
executing this command.
D
BURST LENGTH
OUT
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
DPL
) after the last data input is required for the device
D
OUT
2
D
OUT
3
ISSI
DMD
QMD
) is fixed
) is fixed
03/13/00
Rev. A
®