is42sm16200c Integrated Silicon Solution, Inc., is42sm16200c Datasheet
is42sm16200c
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is42sm16200c Summary of contents
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... Internal dual banks operation. • Burst Read Single Write operation. • Special Function Support. - PASR(Partial Array Self Refresh) - Auto TCSR(Temperature Compensated Self Refresh) • Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge. www.issi.com - dram@issi.com IS42SM16200C IS42RM16200C IS42VM16200C Advanced Information 1 ...
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Figure1: 54Ball FBGA Ball Assignment A VSS B DQ14 C C DQ12 DQ12 D DQ10 E DQ8 F UDQM VSS Rev. 00A | July 2010 DQ15 VSSQ VDDQ DQ13 VDDQ ...
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Table2: Pin Descriptions Pin Pin CLK System Clock CKE Clock Enable /CS Chip Select Bank Address k Add A0~A10 Address Row Address Strobe, /RAS, /CAS, /WE Column Address Strobe, Write Enable LDQM,UDQM Data Input/Output Mask DQ0~DQ15 Data ...
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Figure2: Functional Block Diagram CLK CLOCK GENERATOR CKE ADDRESS MODE REGISTER /CS /RAS /CAS / /WE Rev. 00A | July 2010 EXTENDED MODE REGISTER TCSR PASR ROW ADDRESS BUFFER & REFRESH COUNTER COUNTER COLUMN ADDRESS BUFFER & BURST COUNTER DQM ...
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Figure3: Simplified State Diagram EXTENDED REGISTER REGISTER POWER DOWN DOWN WRITE CKE ↓ WRITE WRITE SUSPEND CKE CKE ↓ WRITE A WRITE A SUSPEND SUSPEND CKE POWER ON Rev. 00A | July 2010 MODE SET MRS MODE IDLE SET DEEP ...
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Figure4: Mode Register Definition BA A10 Write Burst Mode M6 0 Burst Read and Burst Write 0 1 Burst Read and Single Write Note: M11(BA) must ...
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Figure5: Extended Mode Register BA A10 Driver Strength 0 0 Full Strength 0 1 1/2 Strength 1 0 1/4 Strength 1 1 1/8 Strength Note: E11(BA) must be set to “1” to select Extend ...
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Functional Description In general, this 32Mb SDRAM (1M x 16Bits x 2banks dual-bank DRAM that operates at 3.0V/3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of ...
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Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4. The burst length determines the maximum number of column locations that can be accessed for a given ...
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CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks ...
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Table4: Command Truth Table Function CKEn-1 Command Inhinit (NOP Operation (NOP) H Mode Register Set H Extended Mode Register Set H Active (select bank and H activate row) Read H Read with Autoprecharge H Write H Write with ...
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Table5: Function Truth Table Current State /CS /RAS /CAS Idle ...
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Table5: Function Truth Table Current State /CS /RAS /CAS Write ...
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Table5: Function Truth Table Current State /CS /RAS /CAS echa ging Precharging ...
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Table5: Function Truth Table Current Current State /CS /RAS /CAS Write Recovering with with Auto Precharge ...
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Note : Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge All entries assume that CKE was active during ...
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Table6: CKE Truth Table CKE Current Current Prev Current State /CS Cycle Cycle Self Refresh Refresh Power Down L H ...
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Note : 1. H: Logic High, L: Logic Low, X: Don't care 2. For the given current state CKE must be low in the previous cycle. 3. When CKE has a low to high transition, the clock and other inputs ...
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Table7A: 3.3V Absolute Maximum Rating Parameter Ambient Temperature (Industrial) Ambient Temperature (Commercial) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Short Circuit Output Current Power Dissipation Note : Stresses ...
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Table10A: 3.3V AC Operating Condition (T Parameter Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Output Output ...
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Table7B: 2.5V Absolute Maximum Rating Parameter Ambient Temperature (Industrial) Ambient Temperature (Commercial) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Short Circuit Output Current Power Dissipation Note : Stresses ...
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Table10B: 2.5V AC Operating Condition (T Parameter Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Output Output ...
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Table7C: 1.8V Absolute Maximum Rating Parameter Ambient Temperature (Industrial) Ambient Temperature (Commercial) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Short Circuit Output Current Power Dissipation Note : Stresses ...
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Table10C: 1.8V AC Operating Condition (T Parameter Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Output Output ...
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Table11A: 3.3V DC Characteristic (DC operating conditions unless otherwise noted) P Parameter t Sym S Operating Current ICC1 ICC2P Precharge Standby Current in Power Down Mode ICC2PS ICC2N Precharge Standby Current in Non Power Down Mode ICC2NS ICC3P Active Standby ...
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Table11B: 2.5V DC Characteristic (DC operating conditions unless otherwise noted) Parameter P t Sym S Operating Current ICC1 ICC2P Precharge Standby Current in Power Down Mode ICC2PS ICC2N Precharge Standby Current in Non Power Down Mode ICC2NS ICC3P Active Standby ...
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Table11C: 1.8V DC Characteristic (DC operating conditions unless otherwise noted) Parameter Sym Operating Current ICC1 ICC2P Precharge Standby Current in Power Down Mode ICC2PS ICC2N ICC2N Precharge Standby Current in Non Power Down Mode ICC2NS ICC3P Active ...
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Table12: AC Characteristic (AC operation conditions unless otherwise noted) Parameter CLK Cycle Time Access time from CLK (pos. edge CLK High-Level Width CLK Low-Level Width CKE Setup Time ...
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Note : 1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be ...
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... Deep Power Down Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock, while CKE is low ...
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Figure7: Deep Power Down Mode Entry CLK CKE /CS /RAS / /CAS /WE Precharge if needed Figure8: Deep Power Down Mode Exit CLK CKE /CS /RAS /CAS /WE 100 µ s 100 µ s tRP tRP Deep Power Down Exit ...
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Rev. 00A | July 2010 www.issi.com - dram@issi.com IS42SM/RM/VM16200C Advanced Information 32 ...
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... C) o Speed Order Part No. (ns IS42RM16200C-6BLI 7.5 IS42RM16200C-75BLI C) o Speed Order Part No. (ns) 6 IS42SM16200C-6BLI 7.5 IS42SM16200C-75BLI www.issi.com - dram@issi.com IS42SM/RM/VM16200C Advanced Information Package 54-ball BGA, Lead-free 54-ball BGA, Lead-free Package 54-ball BGA, Lead-free 54-ball BGA, Lead-free Package 54-ball BGA, Lead-free 54-ball BGA, Lead-free 33 ...