is43dr16640a-3dbi Integrated Silicon Solution, Inc., is43dr16640a-3dbi Datasheet
is43dr16640a-3dbi
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is43dr16640a-3dbi Summary of contents
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 • ...
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... VSSQ DQ ground VREF Reference voltage VDDL DLL power supply VSSDL DLL ground ODT On Die Termination Enable NC No connect Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 DQS RDQS VDD VSSQ VSS DQ6 VSSQ DQS VSSQ ...
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... VDDQ DQ power supply VSSQ DQ ground VREF Reference voltage VDDL DLL power supply VSSDL DLL ground ODT On Die Termination Enable NC No connect Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 VDD NC VSS VSSQ B DQ14 VSSQ UDM ...
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... To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 1 at a LOW state (all other inputs may be ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 Active ...
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... Mode register Integrated Silicon Solution, Inc. – www.issi.com – ...
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... Note: All bits in EMR[3] except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR[3]. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 A7 High Temperature Self-Refresh Rate Enable ...
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... Self refresh exit is asynchronous. 8. VREF must be maintained during Self Refresh operation. 9. An refers to the MSBs of addresseses. An=A13 for x8, and An=A12 for x16. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 CS# RAS# CAS# WE# Current ...
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... Name (Functional) Write Enable Write Inhibit Note: 1. Used to mask write data, provided coincident with the corresponding data. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 (3) Command (N) (1) RAS#, CAS#, WE#, CS# Current Cycle ...
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... REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#‐before‐RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing a REFRESH command. This command is nonpersistent, so it must be issued each time a refresh is Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ...
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... ODT turn off time min, tAOF(Min), is when the device starts to turn off the ODT resistance. ODT turn off time max, tAOF(Max) is when the bus is in high impedance. Both are measured from tAOFD. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ...
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... ODT Timing for Precharge Power‐Down Mode Note: Both ODT to Power Down Endtry and Exit Latencies tANPD and tAXPD are not met, therefore Power‐Down Mode timings have to be applied. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ...
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... Parameter VIH(DC) DC input logic HIGH VIL(DC) DC input logic LOW Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ‐1.0 to 2.3 ‐ 0.5 to 2.3 ‐ 0.5 to 2.3 ‐ 0.5 to 2.3 ...
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... The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 DDR2‐533 ...
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... Note: Please refer to AC Overshoot and Undershoot Definition Diagram. AC Overshoot and Undershoot Definition Diagram DDQ Volts ( SSQ Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 V DDQ SSQ Min. 0.5 x VDDQ‐0.125 ...
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... Input Capacitance (all other input‐only pins) Input Capacitance Delta (all other input‐only pins) I/O Capacitance (DQ, DM, DQS, DQS#) I/O Capacitance Delta (DQ, DM, DQS, DQS#) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 Parameter SSTL_18 Parameter ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 Symbol ...
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... For DDR2‐667/800/1066 testing, tCK in the Conditions should be interpreted as tCK(avg). 3. Definitions for IDD: Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 . MRS A12 bit is set to . MRS A12 bit is set to ...
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... IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Parametric Test Condition. 3. IDD parameters are specified with ODT disabled. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ‐37C ‐3D DDR2‐533C ...
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... Data Hold Skew tQHS Factor Clock Half Period tHP Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ‐37C ‐3D ‐25E DDR2‐533C DDR2‐667D ...
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... Impedance from CK/CK# DQS/DQS# Low tLZ(DQS) Impedance from CK/CK# Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ‐37C ‐3D ‐25E DDR2‐533C DDR2‐667D DDR2‐800E DDR2‐800D ...
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... Notes: 1. Input slew rate is 1 V/ns and AC timings are guaranteed for linear signal transitions. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ‐37C ‐3D ‐25E DDR2‐533C ...
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... Supported only for industrial and automotive grades. TOPER must not be violated. Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 ...
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... Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 VDDQ DQ DQS ...
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... IS43DR81280A ‐25EBLI IS43DR16640A ‐25EBLI 5‐5‐5 IS43DR81280A ‐25DBLI 128Mb x 8 IS43DR16640A ‐25DBLI 64Mb x 16 = ‐40°C to +85°C A CL‐t ‐t ...
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... IS43DR81280A, IS43/46DR16640A PACKAGE OUTLINE DRAWING 60-ball FBGA: Fine Pitch Ball Grid Array Outline (x8) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 units (mm) 27 ...
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... IS43DR81280A, IS43/46DR16640A 84-ball FBGA: Fine Pitch Ball Grid Array Outline (x16) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00A, 12/11/2009 28 ...