is43dr16640a-3dbi Integrated Silicon Solution, Inc., is43dr16640a-3dbi Datasheet - Page 19

• Manufacturer Part Number: is43dr16640a-3dbi
• Description: 1gb X8, X16 Ddr2 Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

IS43DR81280A, IS43/46DR16640A
IDD Specifications and Conditions
IDD Measurement Conditions
Notes:
1.
2.
3.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A, 12/11/2009
Symbol Parameter/Condition
IDD3Ps
IDD4W
IDD3Pf
IDD2Q
IDD2N
IDD3N
IDD5D
IDD2P
IDD4R
IDD5B
IDD0
IDD1
IDD6
IDD7
Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#. IDD values must be met with all combinations of EMRS bits 10 and 11.
For DDR2‐667/800/1066 testing, tCK in the Conditions should be interpreted as tCK(avg).
Definitions for IDD:
Operating Current ‐ One bank Active ‐ Precharge:
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING.
Operating Current ‐ One bank Active ‐ Read ‐ Precharge:
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge Power‐Down Current:
Precharge Standby Current:
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge Quiet Standby Current:
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active Power‐Down Current:
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
“0”(Fast Power‐down Exit).
Active Power‐Down Current:
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
“1”(Slow Power‐down Exit).
Active Standby Current:
All banks open;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING.
Operating Current ‐ Burst Read:
All banks open, Continuous burst reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Operating Current ‐ Burst Write:
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is
HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Burst Auto‐Refresh Current:
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
Distributed Refresh Current:
tCK = tCK(IDD); Refresh command frequency satisfying tREFI; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
Self‐Refresh Current:
CK and CK# at 0 V; CKE 0.2 V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING
Operating Bank Interleave Read Current:
1.
2.
3.
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
same as IDD4R;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) ‐ 1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW =
tFAW(IDD), tRCD = 1 x tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
Timing pattern for x8:
Timing patter for x16
a.
b.
c.
d.
a.
b.
c.
d.
DDR2‐533 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
DDR2‐667 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
DDR2‐800 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
DDR2‐1066 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
DDR2‐533 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
DDR2‐667 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
DDR2‐800 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
DDR2‐1066 all bins: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7
RA7 D D D D
.
. MRS A12 bit is set to
. MRS A12 bit is set to
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