m24256-br STMicroelectronics, m24256-br Datasheet - Page 16

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m24256-br

Manufacturer Part Number
m24256-br
Description
512 Kbit And 256 Kbit Serial I2c Bus Eeprom With Three Chip Enable Lines
Manufacturer
STMicroelectronics
Datasheet

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Device operation
3.9
Caution:
16/35
ECC (error correction code) and write cycling
The M24512-W, M24512-R, M24256-BW and M24256-BR devices offer an ECC (error
correction code) logic which compares each 4-byte word with its six associated ECC
EEPROM bits. As a result, if a single bit out of 4 bytes of data happens to be erroneous
during a Read operation, the ECC detects it and replaces it by the correct value. The read
reliability is therefore much improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write by word (4 bytes) in order to
benefit from the larger amount of Write cycles.
The M24512-W, M24512-R, M24256-BW and M24256-BR devices are qualified at 1 million
(1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-
bytes.
Note that the M24512-W and M24512-R in SO8 Wide package (MW) are offered with either
the previous die qualified at 100.000 Write cycles or the new die (qualified at 1 Million Write
cycles). The two dice are distinguished by their respective process letter: "V" for the
previous die and " A" for the new die. Please contact your nearest ST sales office for more
information.
Figure 8.
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write
(cont'd)
Write Mode sequences with WC = 0 (data write enabled)
ACK
Dev sel
Dev sel
M24512-W, M24512-R, M24512-HR, M24256-BW, M24256-BR
Data in N
R/W
R/W
ACK
ACK
ACK
Byte addr
Byte addr
ACK
ACK
Byte addr
Byte addr
ACK
ACK
Data in 1
Data in
ACK
ACK
AI01106d
Data in 2

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